Commit | Line | Data |
---|---|---|
51129dfe IS |
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296 | (pin Oval[A]Pad_1727.2x1727.2_um 21 0 -25400)\r | |
297 | (pin Oval[A]Pad_1727.2x1727.2_um 20 2540 -22860)\r | |
298 | (pin Oval[A]Pad_1727.2x1727.2_um 19 0 -22860)\r | |
299 | (pin Oval[A]Pad_1727.2x1727.2_um 18 2540 -20320)\r | |
300 | (pin Oval[A]Pad_1727.2x1727.2_um 17 0 -20320)\r | |
301 | (pin Oval[A]Pad_1727.2x1727.2_um 16 2540 -17780)\r | |
302 | (pin Oval[A]Pad_1727.2x1727.2_um 15 0 -17780)\r | |
303 | (pin Oval[A]Pad_1727.2x1727.2_um 14 2540 -15240)\r | |
304 | (pin Oval[A]Pad_1727.2x1727.2_um 13 0 -15240)\r | |
305 | (pin Oval[A]Pad_1727.2x1727.2_um 12 2540 -12700)\r | |
306 | (pin Oval[A]Pad_1727.2x1727.2_um 11 0 -12700)\r | |
307 | (pin Oval[A]Pad_1727.2x1727.2_um 10 2540 -10160)\r | |
308 | (pin Oval[A]Pad_1727.2x1727.2_um 9 0 -10160)\r | |
309 | (pin Oval[A]Pad_1727.2x1727.2_um 8 2540 -7620)\r | |
310 | (pin Oval[A]Pad_1727.2x1727.2_um 7 0 -7620)\r | |
311 | (pin Oval[A]Pad_1727.2x1727.2_um 6 2540 -5080)\r | |
312 | (pin Oval[A]Pad_1727.2x1727.2_um 5 0 -5080)\r | |
313 | (pin Oval[A]Pad_1727.2x1727.2_um 4 2540 -2540)\r | |
314 | (pin Oval[A]Pad_1727.2x1727.2_um 3 0 -2540)\r | |
315 | (pin Oval[A]Pad_1727.2x1727.2_um 2 2540 0)\r | |
316 | (pin Rect[A]Pad_1727.2x1727.2_um 1 0 0)\r | |
317 | )\r | |
318 | (image "footprints:640456-8"\r | |
319 | (outline (path signal 152.4 18161 -1905 18088.2 -2128.95 17897.7 -2267.35 17662.3 -2267.35\r | |
320 | 17471.8 -2128.95 17399 -1905 17471.8 -1681.05 17662.3 -1542.65\r | |
321 | 17897.7 -1542.65 18088.2 -1681.05 18161 -1905))\r | |
322 | (outline (path signal 152.4 20193 0 20120.2 -223.946 19929.7 -362.353 19694.3 -362.353\r | |
323 | 19503.8 -223.946 19431 0 19503.8 223.946 19694.3 362.353\r | |
324 | 19929.7 362.353 20120.2 223.946 20193 0))\r | |
325 | (outline (path signal 152.4 20193 0 20120.2 -223.946 19929.7 -362.353 19694.3 -362.353\r | |
326 | 19503.8 -223.946 19431 0 19503.8 223.946 19694.3 362.353\r | |
327 | 19929.7 362.353 20120.2 223.946 20193 0))\r | |
328 | (outline (path signal 152.4 19050 3302 -1270 3302))\r | |
329 | (outline (path signal 152.4 19050 -2413 19050 3302))\r | |
330 | (outline (path signal 152.4 -1270 -2413 19050 -2413))\r | |
331 | (outline (path signal 152.4 -1270 3302 -1270 -2413))\r | |
332 | (outline (path signal 152.4 19304 3556 -1524 3556))\r | |
333 | (outline (path signal 152.4 19304 -2667 19304 3556))\r | |
334 | (outline (path signal 152.4 -1524 -2667 19304 -2667))\r | |
335 | (outline (path signal 152.4 -1524 3556 -1524 -2667))\r | |
336 | (outline (path signal 152.4 -1270 3302 -1270 -2413))\r | |
337 | (outline (path signal 152.4 19050 3302 -1270 3302))\r | |
338 | (outline (path signal 152.4 19050 -2413 19050 3302))\r | |
339 | (outline (path signal 152.4 -1270 -2413 19050 -2413))\r | |
340 | (outline (path signal 152.4 -1397 3429 -1397 -2540))\r | |
341 | (outline (path signal 152.4 19177 3429 -1397 3429))\r | |
342 | (outline (path signal 152.4 19177 -2540 19177 3429))\r | |
343 | (outline (path signal 152.4 -1397 -2540 19177 -2540))\r | |
344 | (pin Round[A]Pad_1524_um 8 0 0)\r | |
345 | (pin Round[A]Pad_1524_um 7 2540 0)\r | |
346 | (pin Round[A]Pad_1524_um 6 5080 0)\r | |
347 | (pin Round[A]Pad_1524_um 5 7620 0)\r | |
348 | (pin Round[A]Pad_1524_um 4 10160 0)\r | |
349 | (pin Round[A]Pad_1524_um 3 12700 0)\r | |
350 | (pin Round[A]Pad_1524_um 2 15240 0)\r | |
351 | (pin Round[A]Pad_1524_um 1 17780 0)\r | |
352 | )\r | |
353 | (image "footprints:640456-8::1"\r | |
354 | (outline (path signal 152.4 -1397 -2540 19177 -2540))\r | |
355 | (outline (path signal 152.4 19177 -2540 19177 3429))\r | |
356 | (outline (path signal 152.4 19177 3429 -1397 3429))\r | |
357 | (outline (path signal 152.4 -1397 3429 -1397 -2540))\r | |
358 | (outline (path signal 152.4 -1270 -2413 19050 -2413))\r | |
359 | (outline (path signal 152.4 19050 -2413 19050 3302))\r | |
360 | (outline (path signal 152.4 19050 3302 -1270 3302))\r | |
361 | (outline (path signal 152.4 -1270 3302 -1270 -2413))\r | |
362 | (outline (path signal 152.4 -1524 3556 -1524 -2667))\r | |
363 | (outline (path signal 152.4 -1524 -2667 19304 -2667))\r | |
364 | (outline (path signal 152.4 19304 -2667 19304 3556))\r | |
365 | (outline (path signal 152.4 19304 3556 -1524 3556))\r | |
366 | (outline (path signal 152.4 -1270 3302 -1270 -2413))\r | |
367 | (outline (path signal 152.4 -1270 -2413 19050 -2413))\r | |
368 | (outline (path signal 152.4 19050 -2413 19050 3302))\r | |
369 | (outline (path signal 152.4 19050 3302 -1270 3302))\r | |
370 | (outline (path signal 152.4 20193 0 20120.2 -223.946 19929.7 -362.353 19694.3 -362.353\r | |
371 | 19503.8 -223.946 19431 0 19503.8 223.946 19694.3 362.353\r | |
372 | 19929.7 362.353 20120.2 223.946 20193 0))\r | |
373 | (outline (path signal 152.4 20193 0 20120.2 -223.946 19929.7 -362.353 19694.3 -362.353\r | |
374 | 19503.8 -223.946 19431 0 19503.8 223.946 19694.3 362.353\r | |
375 | 19929.7 362.353 20120.2 223.946 20193 0))\r | |
376 | (outline (path signal 152.4 18161 -1905 18088.2 -2128.95 17897.7 -2267.35 17662.3 -2267.35\r | |
377 | 17471.8 -2128.95 17399 -1905 17471.8 -1681.05 17662.3 -1542.65\r | |
378 | 17897.7 -1542.65 18088.2 -1681.05 18161 -1905))\r | |
379 | (pin Round[A]Pad_1524_um 1 17780 0)\r | |
380 | (pin Round[A]Pad_1524_um 2 15240 0)\r | |
381 | (pin Round[A]Pad_1524_um 3 12700 0)\r | |
382 | (pin Round[A]Pad_1524_um 4 10160 0)\r | |
383 | (pin Round[A]Pad_1524_um 5 7620 0)\r | |
384 | (pin Round[A]Pad_1524_um 6 5080 0)\r | |
385 | (pin Round[A]Pad_1524_um 7 2540 0)\r | |
386 | (pin Round[A]Pad_1524_um 8 0 0)\r | |
387 | )\r | |
388 | (image "digikey-footprints:SIP-9_P2.54mm"\r | |
389 | (outline (path signal 50 21820 -1500 -1490 -1500))\r | |
390 | (outline (path signal 50 21820 1500 -1490 1500))\r | |
391 | (outline (path signal 50 21820 1500 21820 -1500))\r | |
392 | (outline (path signal 50 -1490 1500 -1490 -1500))\r | |
393 | (outline (path signal 100 21700 -1400 21200 -1400))\r | |
394 | (outline (path signal 100 21700 -1400 21700 -900))\r | |
395 | (outline (path signal 100 21700 1400 21700 900))\r | |
396 | (outline (path signal 100 21700 1400 21200 1400))\r | |
397 | (outline (path signal 100 -900 1400 -1400 1400))\r | |
398 | (outline (path signal 100 -1400 1400 -1400 -1400))\r | |
399 | (outline (path signal 100 -1400 -1400 -900 -1400))\r | |
400 | (outline (path signal 100 21570 1250 21570 -1250))\r | |
401 | (outline (path signal 100 -1240 1250 -1240 -1250))\r | |
402 | (outline (path signal 100 -1240 -1250 21570 -1250))\r | |
403 | (outline (path signal 100 -1240 1250 21570 1250))\r | |
404 | (pin Rect[A]Pad_1810x1810_um 1 0 0)\r | |
405 | (pin Round[A]Pad_1810_um 2 2540 0)\r | |
406 | (pin Round[A]Pad_1810_um 3 5080 0)\r | |
407 | (pin Round[A]Pad_1810_um 4 7620 0)\r | |
408 | (pin Round[A]Pad_1810_um 5 10160 0)\r | |
409 | (pin Round[A]Pad_1810_um 6 12700 0)\r | |
410 | (pin Round[A]Pad_1810_um 7 15240 0)\r | |
411 | (pin Round[A]Pad_1810_um 8 17780 0)\r | |
412 | (pin Round[A]Pad_1810_um 9 20320 0)\r | |
413 | )\r | |
414 | (image "digikey-footprints:SIP-9_P2.54mm::1"\r | |
415 | (outline (path signal 100 -1240 1250 21570 1250))\r | |
416 | (outline (path signal 100 -1240 -1250 21570 -1250))\r | |
417 | (outline (path signal 100 -1240 1250 -1240 -1250))\r | |
418 | (outline (path signal 100 21570 1250 21570 -1250))\r | |
419 | (outline (path signal 100 -1400 -1400 -900 -1400))\r | |
420 | (outline (path signal 100 -1400 1400 -1400 -1400))\r | |
421 | (outline (path signal 100 -900 1400 -1400 1400))\r | |
422 | (outline (path signal 100 21700 1400 21200 1400))\r | |
423 | (outline (path signal 100 21700 1400 21700 900))\r | |
424 | (outline (path signal 100 21700 -1400 21700 -900))\r | |
425 | (outline (path signal 100 21700 -1400 21200 -1400))\r | |
426 | (outline (path signal 50 -1490 1500 -1490 -1500))\r | |
427 | (outline (path signal 50 21820 1500 21820 -1500))\r | |
428 | (outline (path signal 50 21820 1500 -1490 1500))\r | |
429 | (outline (path signal 50 21820 -1500 -1490 -1500))\r | |
430 | (pin Round[A]Pad_1810_um 9 20320 0)\r | |
431 | (pin Round[A]Pad_1810_um 8 17780 0)\r | |
432 | (pin Round[A]Pad_1810_um 7 15240 0)\r | |
433 | (pin Round[A]Pad_1810_um 6 12700 0)\r | |
434 | (pin Round[A]Pad_1810_um 5 10160 0)\r | |
435 | (pin Round[A]Pad_1810_um 4 7620 0)\r | |
436 | (pin Round[A]Pad_1810_um 3 5080 0)\r | |
437 | (pin Round[A]Pad_1810_um 2 2540 0)\r | |
438 | (pin Rect[A]Pad_1810x1810_um 1 0 0)\r | |
439 | )\r | |
440 | (padstack Round[A]Pad_1524_um\r | |
441 | (shape (circle F.Cu 1524))\r | |
442 | (shape (circle B.Cu 1524))\r | |
443 | (attach off)\r | |
444 | )\r | |
445 | (padstack Round[A]Pad_1676.4_um\r | |
446 | (shape (circle F.Cu 1676.4))\r | |
447 | (shape (circle B.Cu 1676.4))\r | |
448 | (attach off)\r | |
449 | )\r | |
450 | (padstack Round[A]Pad_1810_um\r | |
451 | (shape (circle F.Cu 1810))\r | |
452 | (shape (circle B.Cu 1810))\r | |
453 | (attach off)\r | |
454 | )\r | |
455 | (padstack Oval[A]Pad_1727.2x1727.2_um\r | |
456 | (shape (path F.Cu 1727.2 0 0 0 0))\r | |
457 | (shape (path B.Cu 1727.2 0 0 0 0))\r | |
458 | (attach off)\r | |
459 | )\r | |
460 | (padstack Rect[A]Pad_1676.4x1676.4_um\r | |
461 | (shape (rect F.Cu -838.2 -838.2 838.2 838.2))\r | |
462 | (shape (rect B.Cu -838.2 -838.2 838.2 838.2))\r | |
463 | (attach off)\r | |
464 | )\r | |
465 | (padstack Rect[A]Pad_1727.2x1727.2_um\r | |
466 | (shape (rect F.Cu -863.6 -863.6 863.6 863.6))\r | |
467 | (shape (rect B.Cu -863.6 -863.6 863.6 863.6))\r | |
468 | (attach off)\r | |
469 | )\r | |
470 | (padstack Rect[A]Pad_1810x1810_um\r | |
471 | (shape (rect F.Cu -905 -905 905 905))\r | |
472 | (shape (rect B.Cu -905 -905 905 905))\r | |
473 | (attach off)\r | |
474 | )\r | |
475 | (padstack "Via[0-1]_600:400_um"\r | |
476 | (shape (circle F.Cu 600))\r | |
477 | (shape (circle B.Cu 600))\r | |
478 | (attach off)\r | |
479 | )\r | |
480 | )\r | |
481 | (network\r | |
482 | (net SR1_CLR\r | |
483 | (pins U2-9 P8-17)\r | |
484 | )\r | |
485 | (net SR1_SHLD\r | |
486 | (pins U2-7 P8-15)\r | |
487 | )\r | |
488 | (net SR1_CLK\r | |
489 | (pins U2-3 P8-11)\r | |
490 | )\r | |
491 | (net SR1_CLKINH\r | |
492 | (pins U2-5 P8-5)\r | |
493 | )\r | |
494 | (net SR1_QH_T\r | |
495 | (pins U1-2 P8-4)\r | |
496 | )\r | |
497 | (net PGND\r | |
498 | (pins U8-8 U8-1 U7-1 U7-8 U6-8 U6-1 U5-1 U5-8 U4-8 U4-1 U3-1 U3-8 U2-13 U2-8\r | |
499 | U1-8 U1-13 P8-2 P8-1 P9-46 P9-45 P9-44 P9-43 P9-2 P9-1 RN3-1)\r | |
500 | )\r | |
501 | (net 5v\r | |
502 | (pins U8-16 U7-16 U6-16 U5-16 U4-16 U3-16 U2-16 U1-1 P9-8 P9-7 P9-6 P9-5)\r | |
503 | )\r | |
504 | (net BB3.3\r | |
505 | (pins U2-1 U1-16)\r | |
506 | )\r | |
507 | (net SR1_QH\r | |
508 | (pins U3-13 U1-3)\r | |
509 | )\r | |
510 | (net SR1_CLR_T\r | |
511 | (pins U8-9 U7-9 U6-9 U5-9 U4-9 U3-9 U2-10)\r | |
512 | )\r | |
513 | (net SR1_SHLD_T\r | |
514 | (pins U8-15 U7-15 U6-15 U5-15 U4-15 U3-15 U2-6)\r | |
515 | )\r | |
516 | (net SR1_CLKINH_T\r | |
517 | (pins U8-6 U7-6 U6-6 U5-6 U4-6 U3-6 U2-4)\r | |
518 | )\r | |
519 | (net SR1_CLK_T\r | |
520 | (pins U8-7 U7-7 U6-7 U5-7 U4-7 U3-7 U2-2)\r | |
521 | )\r | |
522 | (net 7SEG_CLK\r | |
523 | (pins U2-11 P8-45)\r | |
524 | )\r | |
525 | (net 7SEG_DIO\r | |
526 | (pins U2-14 P8-43)\r | |
527 | )\r | |
528 | (net SR6_QH_T\r | |
529 | (pins U1-15 P8-18)\r | |
530 | )\r | |
531 | (net SR5_QH_T\r | |
532 | (pins U1-12 P8-16)\r | |
533 | )\r | |
534 | (net SR4_QH_T\r | |
535 | (pins U1-10 P8-14)\r | |
536 | )\r | |
537 | (net SR3_QH_T\r | |
538 | (pins U1-6 P8-12)\r | |
539 | )\r | |
540 | (net +3V3\r | |
541 | (pins P9-4 P9-3)\r | |
542 | )\r | |
543 | (net SR2_QH\r | |
544 | (pins U7-13 U1-5)\r | |
545 | )\r | |
546 | (net SR3_QH\r | |
547 | (pins U8-13 U1-7)\r | |
548 | )\r | |
549 | (net SR4_QH\r | |
550 | (pins U6-13 U1-9)\r | |
551 | )\r | |
552 | (net SR5_QH\r | |
553 | (pins U5-13 U1-11)\r | |
554 | )\r | |
555 | (net SR6_QH\r | |
556 | (pins U4-13 U1-14)\r | |
557 | )\r | |
558 | (class kicad_default "" +3V3 /a1 /a2 /a3 /a4 /a5 /a6 /a7 /a8 /b1 /b2 /b3\r | |
559 | /b4 /b5 /b6 /b7 /b8 /c1 /c2 /c3 /c4 /c5 /c6 /c7 /c8 /d1 /d2 /d3 /d4\r | |
560 | /d5 /d6 /d7 /d8 /e1 /e2 /e3 /e4 /e5 /e6 /e7 /e8 /f1 /f2 /f3 /f4 /f5\r | |
561 | /f6 /f7 /f8 5v 7SEG_CLK 7SEG_CLK_T 7SEG_DIO 7SEG_DIO_T BB3.3 GNDA_ADC\r | |
562 | "Net-(P8-Pad10)" "Net-(P8-Pad13)" "Net-(P8-Pad19)" "Net-(P8-Pad20)"\r | |
563 | "Net-(P8-Pad21)" "Net-(P8-Pad22)" "Net-(P8-Pad23)" "Net-(P8-Pad24)"\r | |
564 | "Net-(P8-Pad25)" "Net-(P8-Pad26)" "Net-(P8-Pad27)" "Net-(P8-Pad28)"\r | |
565 | "Net-(P8-Pad29)" "Net-(P8-Pad3)" "Net-(P8-Pad30)" "Net-(P8-Pad31)" "Net-(P8-Pad32)"\r | |
566 | "Net-(P8-Pad33)" "Net-(P8-Pad34)" "Net-(P8-Pad35)" "Net-(P8-Pad36)"\r | |
567 | "Net-(P8-Pad37)" "Net-(P8-Pad38)" "Net-(P8-Pad39)" "Net-(P8-Pad40)"\r | |
568 | "Net-(P8-Pad41)" "Net-(P8-Pad42)" "Net-(P8-Pad44)" "Net-(P8-Pad46)"\r | |
569 | "Net-(P8-Pad7)" "Net-(P8-Pad8)" "Net-(P8-Pad9)" "Net-(P9-Pad11)" "Net-(P9-Pad12)"\r | |
570 | "Net-(P9-Pad13)" "Net-(P9-Pad14)" "Net-(P9-Pad15)" "Net-(P9-Pad16)"\r | |
571 | "Net-(P9-Pad17)" "Net-(P9-Pad18)" "Net-(P9-Pad19)" "Net-(P9-Pad20)"\r | |
572 | "Net-(P9-Pad21)" "Net-(P9-Pad22)" "Net-(P9-Pad23)" "Net-(P9-Pad24)"\r | |
573 | "Net-(P9-Pad25)" "Net-(P9-Pad26)" "Net-(P9-Pad27)" "Net-(P9-Pad28)"\r | |
574 | "Net-(P9-Pad29)" "Net-(P9-Pad30)" "Net-(P9-Pad31)" "Net-(P9-Pad33)"\r | |
575 | "Net-(P9-Pad35)" "Net-(P9-Pad36)" "Net-(P9-Pad37)" "Net-(P9-Pad38)"\r | |
576 | "Net-(P9-Pad39)" "Net-(P9-Pad40)" "Net-(P9-Pad41)" "Net-(P9-Pad42)"\r | |
577 | "Net-(R1-Pad2)" "Net-(R10-Pad2)" "Net-(R11-Pad2)" "Net-(R12-Pad2)" "Net-(R13-Pad2)"\r | |
578 | "Net-(R14-Pad2)" "Net-(R15-Pad2)" "Net-(R16-Pad2)" "Net-(R17-Pad2)"\r | |
579 | "Net-(R18-Pad2)" "Net-(R19-Pad2)" "Net-(R2-Pad2)" "Net-(R20-Pad2)" "Net-(R21-Pad2)"\r | |
580 | "Net-(R22-Pad2)" "Net-(R23-Pad2)" "Net-(R24-Pad2)" "Net-(R25-Pad2)"\r | |
581 | "Net-(R26-Pad2)" "Net-(R27-Pad2)" "Net-(R28-Pad2)" "Net-(R29-Pad2)"\r | |
582 | "Net-(R3-Pad2)" "Net-(R30-Pad2)" "Net-(R31-Pad2)" "Net-(R32-Pad2)" "Net-(R33-Pad2)"\r | |
583 | "Net-(R34-Pad2)" "Net-(R35-Pad2)" "Net-(R36-Pad2)" "Net-(R37-Pad2)"\r | |
584 | "Net-(R38-Pad2)" "Net-(R39-Pad2)" "Net-(R4-Pad2)" "Net-(R40-Pad2)" "Net-(R41-Pad2)"\r | |
585 | "Net-(R42-Pad2)" "Net-(R43-Pad2)" "Net-(R44-Pad2)" "Net-(R45-Pad2)"\r | |
586 | "Net-(R46-Pad2)" "Net-(R47-Pad2)" "Net-(R48-Pad2)" "Net-(R5-Pad2)" "Net-(R6-Pad2)"\r | |
587 | "Net-(R7-Pad2)" "Net-(R8-Pad2)" "Net-(R9-Pad2)" "Net-(RN1-Pad1)" "Net-(RN1-Pad2)"\r | |
588 | "Net-(RN1-Pad3)" "Net-(RN1-Pad4)" "Net-(RN1-Pad5)" "Net-(RN1-Pad6)"\r | |
589 | "Net-(RN1-Pad7)" "Net-(RN1-Pad8)" "Net-(RN1-Pad9)" "Net-(RN2-Pad1)"\r | |
590 | "Net-(RN2-Pad2)" "Net-(RN2-Pad3)" "Net-(RN2-Pad4)" "Net-(RN2-Pad5)"\r | |
591 | "Net-(RN2-Pad6)" "Net-(RN2-Pad7)" "Net-(RN2-Pad8)" "Net-(RN2-Pad9)"\r | |
592 | "Net-(RN3-Pad2)" "Net-(RN3-Pad3)" "Net-(RN3-Pad4)" "Net-(RN3-Pad5)"\r | |
593 | "Net-(RN3-Pad6)" "Net-(RN3-Pad7)" "Net-(RN3-Pad8)" "Net-(RN3-Pad9)"\r | |
594 | "Net-(RN4-Pad1)" "Net-(RN4-Pad2)" "Net-(RN4-Pad3)" "Net-(RN4-Pad4)"\r | |
595 | "Net-(RN4-Pad5)" "Net-(RN4-Pad6)" "Net-(RN4-Pad7)" "Net-(RN4-Pad8)"\r | |
596 | "Net-(RN4-Pad9)" "Net-(RN5-Pad1)" "Net-(RN5-Pad2)" "Net-(RN5-Pad3)"\r | |
597 | "Net-(RN5-Pad4)" "Net-(RN5-Pad5)" "Net-(RN5-Pad6)" "Net-(RN5-Pad7)"\r | |
598 | "Net-(RN5-Pad8)" "Net-(RN5-Pad9)" "Net-(RN6-Pad1)" "Net-(RN6-Pad2)"\r | |
599 | "Net-(RN6-Pad3)" "Net-(RN6-Pad4)" "Net-(RN6-Pad5)" "Net-(RN6-Pad6)"\r | |
600 | "Net-(RN6-Pad7)" "Net-(RN6-Pad8)" "Net-(RN6-Pad9)" PGND PWR_BUT SR1_CLK\r | |
601 | SR1_CLKINH SR1_CLKINH_T SR1_CLK_T SR1_CLR SR1_CLR_T SR1_QH SR1_QH_T\r | |
602 | SR1_SHLD SR1_SHLD_T SR2_QH SR2_QH_T SR2_QH__T SR3_QH SR3_QH_T SR4_QH\r | |
603 | SR4_QH_T SR5_QH SR5_QH_T SR6_QH SR6_QH_T SYS_RESETN VDD_ADC a1r a2r\r | |
604 | a3r a4r a5r a6r a7r a8r b1r b2r b3r b4r b5r b6r b7r b8r c1r c2r c3r\r | |
605 | c4r c5r c6r c7r c8r d1r d2r d3r d4r d5r d6r d7r d8r e1r e2r e3r e4r\r | |
606 | e5r e6r e7r e8r f1r f2r f3r f4r f5r f6r f7r f8r\r | |
607 | (circuit\r | |
608 | (use_via Via[0-1]_600:400_um)\r | |
609 | )\r | |
610 | (rule\r | |
611 | (width 250)\r | |
612 | (clearance 200.1)\r | |
613 | )\r | |
614 | )\r | |
615 | )\r | |
616 | (wiring\r | |
617 | )\r | |
618 | )\r |