| 1 | /* $OpenBSD: omap4.c,v 1.3 2013/11/06 19:03:07 syl Exp $ */ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org> |
| 5 | * |
| 6 | * Permission to use, copy, modify, and distribute this software for any |
| 7 | * purpose with or without fee is hereby granted, provided that the above |
| 8 | * copyright notice and this permission notice appear in all copies. |
| 9 | * |
| 10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 17 | */ |
| 18 | |
| 19 | #include <sys/param.h> |
| 20 | #include <sys/systm.h> |
| 21 | #include <sys/device.h> |
| 22 | |
| 23 | #include <machine/bus.h> |
| 24 | |
| 25 | #include <armv7/armv7/armv7var.h> |
| 26 | |
| 27 | #define OMAPID_ADDR 0x4a002000 |
| 28 | #define OMAPID_SIZE 0x1000 |
| 29 | |
| 30 | #define WD_ADDR 0x4a314000 |
| 31 | #define WD_SIZE 0x80 |
| 32 | |
| 33 | #define GPIOx_SIZE 0x1000 |
| 34 | #define GPIO1_ADDR 0x4a310000 |
| 35 | #define GPIO2_ADDR 0x48055000 |
| 36 | #define GPIO3_ADDR 0x48057000 |
| 37 | #define GPIO4_ADDR 0x48059000 |
| 38 | #define GPIO5_ADDR 0x4805b000 |
| 39 | #define GPIO6_ADDR 0x4805d000 |
| 40 | |
| 41 | #define GPIO1_IRQ 29 |
| 42 | #define GPIO2_IRQ 30 |
| 43 | #define GPIO3_IRQ 31 |
| 44 | #define GPIO4_IRQ 32 |
| 45 | #define GPIO5_IRQ 33 |
| 46 | #define GPIO6_IRQ 34 |
| 47 | |
| 48 | #define UARTx_SIZE 0x400 |
| 49 | #define UART1_ADDR 0x4806A000 |
| 50 | #define UART2_ADDR 0x4806C000 |
| 51 | #define UART3_ADDR 0x48020000 |
| 52 | #define UART4_ADDR 0x4806E000 |
| 53 | |
| 54 | #define UART1_IRQ 72 |
| 55 | #define UART2_IRQ 73 |
| 56 | #define UART3_IRQ 74 |
| 57 | #define UART4_IRQ 70 |
| 58 | |
| 59 | #define HSMMCx_SIZE 0x200 |
| 60 | #define HSMMC1_ADDR 0x4809c100 |
| 61 | #define HSMMC1_IRQ 83 |
| 62 | |
| 63 | #define PRM_ADDR 0x4a306000 |
| 64 | #define PRM_SIZE 0x2000 |
| 65 | #define CM1_ADDR 0x4a004000 |
| 66 | #define CM1_SIZE 0x1000 |
| 67 | #define CM2_ADDR 0x4a008000 |
| 68 | #define CM2_SIZE 0x2000 |
| 69 | #define SCRM_ADDR 0x4a30a000 |
| 70 | #define SCRM_SIZE 0x1000 |
| 71 | #define PCNF1_ADDR 0x4a100000 |
| 72 | #define PCNF1_SIZE 0x1000 |
| 73 | #define PCNF2_ADDR 0x4a31e000 |
| 74 | #define PCNF2_SIZE 0x1000 |
| 75 | |
| 76 | #define HSUSBHOST_ADDR 0x4a064000 |
| 77 | #define HSUSBHOST_SIZE 0x800 |
| 78 | #define USBEHCI_ADDR 0x4a064c00 |
| 79 | #define USBEHCI_SIZE 0x400 |
| 80 | #define USBOHCI_ADDR 0x4a064800 |
| 81 | #define USBOHCI_SIZE 0x400 |
| 82 | #define USBEHCI_IRQ 77 |
| 83 | |
| 84 | struct armv7_dev omap4_devs[] = { |
| 85 | |
| 86 | /* |
| 87 | * Power, Reset and Clock Manager |
| 88 | */ |
| 89 | |
| 90 | { .name = "prcm", |
| 91 | .unit = 0, |
| 92 | .mem = { |
| 93 | { PRM_ADDR, PRM_SIZE }, |
| 94 | { CM1_ADDR, CM1_SIZE }, |
| 95 | { CM2_ADDR, CM2_SIZE }, |
| 96 | }, |
| 97 | }, |
| 98 | |
| 99 | /* |
| 100 | * OMAP identification registers/fuses |
| 101 | */ |
| 102 | |
| 103 | { .name = "omapid", |
| 104 | .unit = 0, |
| 105 | .mem = { { OMAPID_ADDR, OMAPID_SIZE } }, |
| 106 | }, |
| 107 | |
| 108 | /* |
| 109 | * GPIO |
| 110 | */ |
| 111 | |
| 112 | { .name = "omgpio", |
| 113 | .unit = 0, |
| 114 | .mem = { { GPIO1_ADDR, GPIOx_SIZE } }, |
| 115 | .irq = { GPIO1_IRQ } |
| 116 | }, |
| 117 | |
| 118 | { .name = "omgpio", |
| 119 | .unit = 1, |
| 120 | .mem = { { GPIO2_ADDR, GPIOx_SIZE } }, |
| 121 | .irq = { GPIO2_IRQ } |
| 122 | }, |
| 123 | |
| 124 | { .name = "omgpio", |
| 125 | .unit = 2, |
| 126 | .mem = { { GPIO3_ADDR, GPIOx_SIZE } }, |
| 127 | .irq = { GPIO3_IRQ } |
| 128 | }, |
| 129 | |
| 130 | { .name = "omgpio", |
| 131 | .unit = 3, |
| 132 | .mem = { { GPIO4_ADDR, GPIOx_SIZE } }, |
| 133 | .irq = { GPIO4_IRQ } |
| 134 | }, |
| 135 | |
| 136 | { .name = "omgpio", |
| 137 | .unit = 4, |
| 138 | .mem = { { GPIO5_ADDR, GPIOx_SIZE } }, |
| 139 | .irq = { GPIO5_IRQ } |
| 140 | }, |
| 141 | |
| 142 | { .name = "omgpio", |
| 143 | .unit = 5, |
| 144 | .mem = { { GPIO6_ADDR, GPIOx_SIZE } }, |
| 145 | .irq = { GPIO6_IRQ } |
| 146 | }, |
| 147 | |
| 148 | /* |
| 149 | * Watchdog Timer |
| 150 | */ |
| 151 | |
| 152 | { .name = "omdog", |
| 153 | .unit = 0, |
| 154 | .mem = { { WD_ADDR, WD_SIZE } } |
| 155 | }, |
| 156 | |
| 157 | /* |
| 158 | * UART |
| 159 | */ |
| 160 | |
| 161 | { .name = "com", |
| 162 | .unit = 2, |
| 163 | .mem = { { UART3_ADDR, UARTx_SIZE } }, |
| 164 | .irq = { UART3_IRQ } |
| 165 | }, |
| 166 | |
| 167 | /* |
| 168 | * MMC |
| 169 | */ |
| 170 | |
| 171 | { .name = "ommmc", |
| 172 | .unit = 0, |
| 173 | .mem = { { HSMMC1_ADDR, HSMMCx_SIZE } }, |
| 174 | .irq = { HSMMC1_IRQ } |
| 175 | }, |
| 176 | |
| 177 | /* |
| 178 | * USB |
| 179 | */ |
| 180 | |
| 181 | { .name = "ehci", |
| 182 | .unit = 0, |
| 183 | .mem = { |
| 184 | { USBEHCI_ADDR, USBEHCI_SIZE }, |
| 185 | { HSUSBHOST_ADDR, HSUSBHOST_SIZE }, |
| 186 | }, |
| 187 | .irq = { USBEHCI_IRQ } |
| 188 | }, |
| 189 | |
| 190 | /* Terminator */ |
| 191 | { .name = NULL, |
| 192 | .unit = 0, |
| 193 | } |
| 194 | }; |
| 195 | |
| 196 | void |
| 197 | omap4_init(void) |
| 198 | { |
| 199 | armv7_set_devs(omap4_devs); |
| 200 | } |