cf3c20ae |
1 | /* $OpenBSD: am335x.c,v 1.7 2014/03/18 07:34:17 syl Exp $ */ |
2 | |
3 | /* |
4 | * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org> |
5 | * Copyright (c) 2013 Raphael Graf <r@undefined.ch> |
6 | * |
7 | * Permission to use, copy, modify, and distribute this software for any |
8 | * purpose with or without fee is hereby granted, provided that the above |
9 | * copyright notice and this permission notice appear in all copies. |
10 | * |
11 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
12 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
13 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
14 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
15 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
16 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
17 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
18 | */ |
19 | |
20 | #include <sys/types.h> |
21 | #include <sys/param.h> |
22 | #include <machine/bus.h> |
23 | |
24 | #include <armv7/armv7/armv7var.h> |
25 | |
26 | #define PRCM_SIZE 0x2000 |
27 | #define PRCM_ADDR 0x44E00000 |
28 | |
29 | #define SCM_SIZE 0x2000 |
30 | #define SCM_ADDR 0x44E10000 |
31 | |
32 | #define INTC_SIZE 0x300 |
33 | #define INTC_ADDR 0x48200000 |
34 | |
35 | #define DMTIMERx_SIZE 0x80 |
36 | #define DMTIMER0_ADDR 0x44E05000 |
37 | #define DMTIMER1_ADDR 0x44E31000 /* 1MS */ |
38 | #define DMTIMER2_ADDR 0x48040000 |
39 | #define DMTIMER3_ADDR 0x48042000 |
40 | #define DMTIMER4_ADDR 0x48044000 |
41 | #define DMTIMER5_ADDR 0x48046000 |
42 | #define DMTIMER6_ADDR 0x48048000 |
43 | #define DMTIMER7_ADDR 0x4804A000 |
44 | #define DMTIMER0_IRQ 66 |
45 | #define DMTIMER1_IRQ 67 |
46 | #define DMTIMER2_IRQ 68 |
47 | #define DMTIMER3_IRQ 69 |
48 | #define DMTIMER4_IRQ 92 |
49 | #define DMTIMER5_IRQ 93 |
50 | #define DMTIMER6_IRQ 94 |
51 | #define DMTIMER7_IRQ 95 |
52 | |
53 | #define WD_SIZE 0x80 |
54 | #define WD_ADDR 0x44E35000 |
55 | #define WD_IRQ 91 |
56 | |
57 | #define GPIOx_SIZE 0x200 |
58 | #define GPIO0_ADDR 0x44E07000 |
59 | #define GPIO1_ADDR 0x4804C000 |
60 | #define GPIO2_ADDR 0x481AC000 |
61 | #define GPIO3_ADDR 0x481AE000 |
62 | #define GPIO0_IRQ 96 |
63 | #define GPIO1_IRQ 98 |
64 | #define GPIO2_IRQ 32 |
65 | #define GPIO3_IRQ 62 |
66 | |
67 | #define TPCC_SIZE 0x100000 |
68 | #define TPCC_ADDR 0x49000000 |
69 | #define TPTC0_ADDR 0x49800000 |
70 | #define TPTC1_ADDR 0x49900000 |
71 | #define TPTC2_ADDR 0x49a00000 |
72 | #define EDMACOMP_IRQ 12 |
73 | #define EDMAMPERR_IRQ 13 |
74 | #define EDMAERR_IRQ 14 |
75 | |
76 | #define UARTx_SIZE 0x90 |
77 | #define UART0_ADDR 0x44E09000 |
78 | #define UART1_ADDR 0x48022000 |
79 | #define UART2_ADDR 0x48024000 |
80 | #define UART3_ADDR 0x481A6000 |
81 | #define UART4_ADDR 0x481A8000 |
82 | #define UART5_ADDR 0x481AA000 |
83 | #define UART0_IRQ 72 |
84 | #define UART1_IRQ 73 |
85 | #define UART2_IRQ 74 |
86 | #define UART3_IRQ 44 |
87 | #define UART4_IRQ 45 |
88 | #define UART5_IRQ 46 |
89 | |
90 | #define HSMMCx_SIZE 0x200 |
91 | #define HSMMC0_ADDR 0x48060100 |
92 | #define HSMMC1_ADDR 0x481d8100 |
93 | #define HSMMC0_IRQ 64 |
94 | #define HSMMC1_IRQ 28 |
95 | |
96 | #define CPSW_SIZE 0x4000 |
97 | #define CPSW_ADDR 0x4A100000 |
98 | #define CPSW_IRQ 40 |
99 | |
100 | #define IICx_SIZE 0x1000 |
101 | #define IIC0_ADDR 0x44e0b000 |
102 | #define IIC1_ADDR 0x4802a000 |
103 | #define IIC2_ADDR 0x4819c000 |
104 | #define IIC0_IRQ 70 |
105 | #define IIC1_IRQ 71 |
106 | #define IIC2_IRQ 30 |
107 | |
108 | struct armv7_dev am335x_devs[] = { |
109 | |
110 | /* |
111 | * Power, Reset and Clock Manager |
112 | */ |
113 | |
114 | { .name = "prcm", |
115 | .unit = 0, |
116 | .mem = { { PRCM_ADDR, PRCM_SIZE } }, |
117 | }, |
118 | |
119 | /* |
120 | * System Control Module |
121 | */ |
122 | |
123 | { .name = "sitaracm", |
124 | .unit = 0, |
125 | .mem = { { SCM_ADDR, SCM_SIZE } }, |
126 | }, |
127 | |
128 | /* |
129 | * Interrupt Controller |
130 | */ |
131 | |
132 | { .name = "intc", |
133 | .unit = 0, |
134 | .mem = { { INTC_ADDR, INTC_SIZE } }, |
135 | }, |
136 | |
137 | /* |
138 | * EDMA Controller |
139 | */ |
140 | { .name = "edma", |
141 | .unit = 0, |
142 | .mem = { { TPCC_ADDR, TPCC_SIZE } }, |
143 | .irq = { EDMACOMP_IRQ } |
144 | }, |
145 | |
146 | /* |
147 | * General Purpose Timers |
148 | */ |
149 | |
150 | { .name = "dmtimer", |
151 | .unit = 0, |
152 | .mem = { { DMTIMER2_ADDR, DMTIMERx_SIZE } }, |
153 | .irq = { DMTIMER2_IRQ } |
154 | }, |
155 | |
156 | { .name = "dmtimer", |
157 | .unit = 1, |
158 | .mem = { { DMTIMER3_ADDR, DMTIMERx_SIZE } }, |
159 | .irq = { DMTIMER3_IRQ } |
160 | }, |
161 | |
162 | /* |
163 | * Watchdog Timer |
164 | */ |
165 | |
166 | { .name = "omdog", |
167 | .unit = 0, |
168 | .mem = { { WD_ADDR, WD_SIZE } } |
169 | }, |
170 | |
171 | /* |
172 | * UART |
173 | */ |
174 | |
175 | { .name = "com", |
176 | .unit = 0, |
177 | .mem = { { UART0_ADDR, UARTx_SIZE } }, |
178 | .irq = { UART0_IRQ } |
179 | }, |
180 | |
181 | /* |
182 | * GPIO |
183 | */ |
184 | |
185 | { .name = "omgpio", |
186 | .unit = 0, |
187 | .mem = { { GPIO0_ADDR, GPIOx_SIZE } }, |
188 | .irq = { GPIO0_IRQ } |
189 | }, |
190 | |
191 | { .name = "omgpio", |
192 | .unit = 1, |
193 | .mem = { { GPIO1_ADDR, GPIOx_SIZE } }, |
194 | .irq = { GPIO1_IRQ } |
195 | }, |
196 | |
197 | { .name = "omgpio", |
198 | .unit = 2, |
199 | .mem = { { GPIO2_ADDR, GPIOx_SIZE } }, |
200 | .irq = { GPIO2_IRQ } |
201 | }, |
202 | |
203 | { .name = "omgpio", |
204 | .unit = 3, |
205 | .mem = { { GPIO3_ADDR, GPIOx_SIZE } }, |
206 | .irq = { GPIO3_IRQ } |
207 | }, |
208 | |
209 | /* |
210 | * IIC |
211 | */ |
212 | |
213 | { .name = "tiiic", |
214 | .unit = 0, |
215 | .mem = { { IIC0_ADDR, IICx_SIZE } }, |
216 | .irq = { IIC0_IRQ } |
217 | }, |
218 | |
219 | { .name = "tiiic", |
220 | .unit = 1, |
221 | .mem = { { IIC1_ADDR, IICx_SIZE } }, |
222 | .irq = { IIC1_IRQ } |
223 | }, |
224 | |
225 | { .name = "tiiic", |
226 | .unit = 2, |
227 | .mem = { { IIC2_ADDR, IICx_SIZE } }, |
228 | .irq = { IIC2_IRQ } |
229 | }, |
230 | |
231 | /* |
232 | * MMC |
233 | */ |
234 | |
235 | { .name = "ommmc", |
236 | .unit = 0, |
237 | .mem = { { HSMMC0_ADDR, HSMMCx_SIZE } }, |
238 | .irq = { HSMMC0_IRQ } |
239 | }, |
240 | |
241 | { .name = "ommmc", |
242 | .unit = 1, |
243 | .mem = { { HSMMC1_ADDR, HSMMCx_SIZE } }, |
244 | .irq = { HSMMC1_IRQ } |
245 | }, |
246 | |
247 | /* cpsw Ethernet */ |
248 | { .name = "cpsw", |
249 | .unit = 0, |
250 | .mem = { { CPSW_ADDR, CPSW_SIZE } }, |
251 | .irq = { CPSW_IRQ } |
252 | }, |
253 | |
254 | /* Terminator */ |
255 | { .name = NULL, |
256 | .unit = 0 |
257 | } |
258 | }; |
259 | |
260 | void |
261 | am335x_init(void) |
262 | { |
263 | armv7_set_devs(am335x_devs); |
264 | } |