cf3c20ae |
1 | /* $OpenBSD: if_cpswreg.h,v 1.6 2016/03/02 01:31:41 canacar Exp $ */ |
2 | |
3 | /*- |
4 | * Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org> |
5 | * All rights reserved. |
6 | * |
7 | * Redistribution and use in source and binary forms, with or without |
8 | * modification, are permitted provided that the following conditions |
9 | * are met: |
10 | * 1. Redistributions of source code must retain the above copyright |
11 | * notice, this list of conditions and the following disclaimer. |
12 | * 2. Redistributions in binary form must reproduce the above copyright |
13 | * notice, this list of conditions and the following disclaimer in the |
14 | * documentation and/or other materials provided with the distribution. |
15 | * |
16 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
17 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
18 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
19 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
20 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
21 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
22 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
23 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
24 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
25 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
26 | * SUCH DAMAGE. |
27 | * |
28 | * $FreeBSD$ |
29 | */ |
30 | |
31 | #ifndef _IF_CPSWREG_H |
32 | #define _IF_CPSWREG_H |
33 | |
34 | #define CPSW_SS_OFFSET 0x0000 |
35 | #define CPSW_SS_IDVER (CPSW_SS_OFFSET + 0x00) |
36 | #define CPSW_SS_IDVER_RTL(_r) (((_r) >> 11) & 0x1f) |
37 | #define CPSW_SS_IDVER_MAJ(_r) (((_r) >> 8) & 0x7) |
38 | #define CPSW_SS_IDVER_MIN(_r) ((_r) & 0xff) |
39 | #define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08) |
40 | #define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C) |
41 | #define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10) |
42 | |
43 | #define CPSW_PORT_OFFSET 0x0100 |
44 | #define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) * 0x100)) |
45 | #define CPSW_PORT_P0_CPDMA_TX_PRI_MAP (CPSW_PORT_OFFSET + 0x01C) |
46 | #define CPSW_PORT_P0_CPDMA_RX_CH_MAP (CPSW_PORT_OFFSET + 0x020) |
47 | #define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) * 0x100)) |
48 | #define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) * 0x100)) |
49 | |
50 | #define CPSW_CPDMA_OFFSET 0x0800 |
51 | #define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04) |
52 | #define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08) |
53 | #define CPSW_CPDMA_RX_CONTROL (CPSW_CPDMA_OFFSET + 0x14) |
54 | #define CPSW_CPDMA_RX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x18) |
55 | #define CPSW_CPDMA_SOFT_RESET (CPSW_CPDMA_OFFSET + 0x1c) |
56 | #define CPSW_CPDMA_DMACONTROL (CPSW_CPDMA_OFFSET + 0x20) |
57 | #define CPSW_CPDMA_DMASTATUS (CPSW_CPDMA_OFFSET + 0x24) |
58 | #define CPSW_CPDMA_RX_BUFFER_OFFSET (CPSW_CPDMA_OFFSET + 0x28) |
59 | #define CPSW_CPDMA_TX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0x80) |
60 | #define CPSW_CPDMA_TX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0x84) |
61 | #define CPSW_CPDMA_TX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0x88) |
62 | #define CPSW_CPDMA_TX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0x8C) |
63 | #define CPSW_CPDMA_CPDMA_EOI_VECTOR (CPSW_CPDMA_OFFSET + 0x94) |
64 | #define CPSW_CPDMA_RX_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xA0) |
65 | #define CPSW_CPDMA_RX_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xA4) |
66 | #define CPSW_CPDMA_RX_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xA8) |
67 | #define CPSW_CPDMA_RX_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xAc) |
68 | #define CPSW_CPDMA_DMA_INTSTAT_RAW (CPSW_CPDMA_OFFSET + 0xB0) |
69 | #define CPSW_CPDMA_DMA_INTSTAT_MASKED (CPSW_CPDMA_OFFSET + 0xB4) |
70 | #define CPSW_CPDMA_DMA_INTMASK_SET (CPSW_CPDMA_OFFSET + 0xB8) |
71 | #define CPSW_CPDMA_DMA_INTMASK_CLEAR (CPSW_CPDMA_OFFSET + 0xBC) |
72 | #define CPSW_CPDMA_RX_FREEBUFFER(p) (CPSW_CPDMA_OFFSET + 0x0e0 + ((p) * 0x04)) |
73 | |
74 | #define CPSW_STATS_OFFSET 0x0900 |
75 | |
76 | #define CPSW_STATERAM_OFFSET 0x0A00 |
77 | #define CPSW_CPDMA_TX_HDP(p) (CPSW_STATERAM_OFFSET + 0x00 + ((p) * 0x04)) |
78 | #define CPSW_CPDMA_RX_HDP(p) (CPSW_STATERAM_OFFSET + 0x20 + ((p) * 0x04)) |
79 | #define CPSW_CPDMA_TX_CP(p) (CPSW_STATERAM_OFFSET + 0x40 + ((p) * 0x04)) |
80 | #define CPSW_CPDMA_RX_CP(p) (CPSW_STATERAM_OFFSET + 0x60 + ((p) * 0x04)) |
81 | |
82 | #define CPSW_CPTS_OFFSET 0x0C00 |
83 | |
84 | #define CPSW_ALE_OFFSET 0x0D00 |
85 | #define CPSW_ALE_CONTROL (CPSW_ALE_OFFSET + 0x08) |
86 | #define CPSW_ALE_TBLCTL (CPSW_ALE_OFFSET + 0x20) |
87 | #define CPSW_ALE_TBLW2 (CPSW_ALE_OFFSET + 0x34) |
88 | #define CPSW_ALE_TBLW1 (CPSW_ALE_OFFSET + 0x38) |
89 | #define CPSW_ALE_TBLW0 (CPSW_ALE_OFFSET + 0x3C) |
90 | #define CPSW_ALE_PORTCTL(p) (CPSW_ALE_OFFSET + 0x40 + ((p) * 0x04)) |
91 | |
92 | #define CPSW_SL_OFFSET 0x0D80 |
93 | #define CPSW_SL_MACCONTROL(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x04) |
94 | #define CPSW_SL_SOFT_RESET(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x0C) |
95 | #define CPSW_SL_RX_MAXLEN(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x10) |
96 | #define CPSW_SL_RX_PRI_MAP(p) (CPSW_SL_OFFSET + (0x40 * (p)) + 0x24) |
97 | |
98 | #define MDIO_OFFSET 0x1000 |
99 | #define MDIOCONTROL (MDIO_OFFSET + 0x04) |
100 | #define MDIOALIVE (MDIO_OFFSET + 0x08) |
101 | #define MDIOLINK (MDIO_OFFSET + 0x0C) |
102 | #define MDIOUSERACCESS0 (MDIO_OFFSET + 0x80) |
103 | #define MDIOUSERPHYSEL0 (MDIO_OFFSET + 0x84) |
104 | |
105 | #define CPSW_WR_OFFSET 0x1200 |
106 | #define CPSW_WR_SOFT_RESET (CPSW_WR_OFFSET + 0x04) |
107 | #define CPSW_WR_CONTROL (CPSW_WR_OFFSET + 0x08) |
108 | #define CPSW_WR_INT_CONTROL (CPSW_WR_OFFSET + 0x0c) |
109 | #define CPSW_WR_C_RX_THRESH_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x10) |
110 | #define CPSW_WR_C_RX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x14) |
111 | #define CPSW_WR_C_TX_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x18) |
112 | #define CPSW_WR_C_MISC_EN(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x1C) |
113 | #define CPSW_WR_C_RX_THRESH_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x40) |
114 | #define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44) |
115 | #define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48) |
116 | #define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C) |
117 | #define CPSW_WR_C_RX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x70) |
118 | #define CPSW_WR_C_TX_IMAX(p) (CPSW_WR_OFFSET + (0x08 * (p)) + 0x74) |
119 | #define CPSW_MISC_HOST_PEND 0x0004 |
120 | |
121 | #define CPSW_CPPI_RAM_OFFSET 0x2000 |
122 | |
123 | #define CPDMA_BD_SOP (1<<15) |
124 | #define CPDMA_BD_EOP (1<<14) |
125 | #define CPDMA_BD_OWNER (1<<13) |
126 | #define CPDMA_BD_EOQ (1<<12) |
127 | #define CPDMA_BD_TDOWNCMPLT (1<<11) |
128 | #define CPDMA_BD_PASSCRC (1<<10) |
129 | #define CPDMA_BD_PKT_ERR_MASK (3<< 4) |
130 | |
131 | struct cpsw_cpdma_bd { |
132 | uint32_t next; |
133 | uint32_t bufptr; |
134 | uint16_t buflen; |
135 | uint16_t bufoff; |
136 | uint16_t pktlen; |
137 | uint16_t flags; |
138 | }; |
139 | |
140 | /* Interrupt offsets */ |
141 | #define CPSW_INTROFF_RXTH 0 |
142 | #define CPSW_INTROFF_RX 1 |
143 | #define CPSW_INTROFF_TX 2 |
144 | #define CPSW_INTROFF_MISC 3 |
145 | |
146 | #endif /*_IF_CPSWREG_H */ |