K2
[bort-board.git] / bbb-bort7.dsn
CommitLineData
51129dfe
IS
1(pcb "C:\Users\kremlin\kicad\projects\bbb-bort\bbb-bort7.dsn"\r
2 (parser\r
3 (string_quote ")\r
4 (space_in_quoted_tokens on)\r
5 (host_cad "KiCad's Pcbnew")\r
6 (host_version "(5.0.1)-3")\r
7 )\r
8 (resolution um 10)\r
9 (unit um)\r
10 (structure\r
11 (layer F.Cu\r
12 (type signal)\r
13 (property\r
14 (index 0)\r
15 )\r
16 )\r
17 (layer B.Cu\r
18 (type signal)\r
19 (property\r
20 (index 1)\r
21 )\r
22 )\r
23 (boundary\r
24 (path pcb 0 149390 -176682 32550.1 -176682 32550.1 -28092.4 149390 -28092.4\r
25 149390 -176682)\r
26 )\r
27 (via "Via[0-1]_600:400_um")\r
28 (rule\r
29 (width 250)\r
30 (clearance 200.1)\r
31 (clearance 200.1 (type default_smd))\r
32 (clearance 50 (type smd_smd))\r
33 )\r
34 )\r
35 (placement\r
36 (component Socket_BeagleBone_Black:Socket_BeagleBone_Black\r
37 (place P8 106210 -91592.4 front 0 (PN BeagleBone_Black_Header))\r
38 (place P9 57950.1 -91592.4 front 0 (PN BeagleBone_Black_Header))\r
39 )\r
40 (component "DIP254P762X508-16N:DIP254P762X508-16N"\r
41 (place U1 96050.1 -54762.4 front 0 (PN 4504))\r
42 )\r
43 (component "DIP254P762X508-16N:DIP254P762X508-16N::1"\r
44 (place U2 132880 -54762.4 front 0 (PN 4504))\r
45 )\r
46 (component "SN74HC166N:DIP254P762X508-16"\r
47 (place U3 115100 -54762.4 front 0 (PN 74166))\r
48 )\r
49 (component "digikey-footprints:PinHeader_2x6_P2.54mm_Vertical_SMD"\r
50 (place J1 47790.1 -50002.4 front 0 (PN 0015912120))\r
51 )\r
52 )\r
53 (library\r
54 (image Socket_BeagleBone_Black:Socket_BeagleBone_Black\r
55 (outline (path signal 150 -1550 1550 -1550 0))\r
56 (outline (path signal 150 1270 -1270 -1270 -1270))\r
57 (outline (path signal 150 1270 1270 1270 -1270))\r
58 (outline (path signal 150 0 1550 -1550 1550))\r
59 (outline (path signal 150 3810 1270 1270 1270))\r
60 (outline (path signal 150 3810 -57150 -1270 -57150))\r
61 (outline (path signal 150 -1270 -57150 -1270 -1270))\r
62 (outline (path signal 150 3810 -57150 3810 1270))\r
63 (outline (path signal 50 -1750 -57650 4300 -57650))\r
64 (outline (path signal 50 -1750 1750 4300 1750))\r
65 (outline (path signal 50 4300 1750 4300 -57650))\r
66 (outline (path signal 50 -1750 1750 -1750 -57650))\r
67 (pin Oval[A]Pad_1727.2x1727.2_um 46 2540 -55880)\r
68 (pin Oval[A]Pad_1727.2x1727.2_um 45 0 -55880)\r
69 (pin Oval[A]Pad_1727.2x1727.2_um 44 2540 -53340)\r
70 (pin Oval[A]Pad_1727.2x1727.2_um 43 0 -53340)\r
71 (pin Oval[A]Pad_1727.2x1727.2_um 42 2540 -50800)\r
72 (pin Oval[A]Pad_1727.2x1727.2_um 41 0 -50800)\r
73 (pin Oval[A]Pad_1727.2x1727.2_um 40 2540 -48260)\r
74 (pin Oval[A]Pad_1727.2x1727.2_um 39 0 -48260)\r
75 (pin Oval[A]Pad_1727.2x1727.2_um 38 2540 -45720)\r
76 (pin Oval[A]Pad_1727.2x1727.2_um 37 0 -45720)\r
77 (pin Oval[A]Pad_1727.2x1727.2_um 36 2540 -43180)\r
78 (pin Oval[A]Pad_1727.2x1727.2_um 35 0 -43180)\r
79 (pin Oval[A]Pad_1727.2x1727.2_um 34 2540 -40640)\r
80 (pin Oval[A]Pad_1727.2x1727.2_um 33 0 -40640)\r
81 (pin Oval[A]Pad_1727.2x1727.2_um 32 2540 -38100)\r
82 (pin Oval[A]Pad_1727.2x1727.2_um 31 0 -38100)\r
83 (pin Oval[A]Pad_1727.2x1727.2_um 30 2540 -35560)\r
84 (pin Oval[A]Pad_1727.2x1727.2_um 29 0 -35560)\r
85 (pin Oval[A]Pad_1727.2x1727.2_um 28 2540 -33020)\r
86 (pin Oval[A]Pad_1727.2x1727.2_um 27 0 -33020)\r
87 (pin Oval[A]Pad_1727.2x1727.2_um 26 2540 -30480)\r
88 (pin Oval[A]Pad_1727.2x1727.2_um 25 0 -30480)\r
89 (pin Oval[A]Pad_1727.2x1727.2_um 24 2540 -27940)\r
90 (pin Oval[A]Pad_1727.2x1727.2_um 23 0 -27940)\r
91 (pin Oval[A]Pad_1727.2x1727.2_um 22 2540 -25400)\r
92 (pin Oval[A]Pad_1727.2x1727.2_um 21 0 -25400)\r
93 (pin Oval[A]Pad_1727.2x1727.2_um 20 2540 -22860)\r
94 (pin Oval[A]Pad_1727.2x1727.2_um 19 0 -22860)\r
95 (pin Oval[A]Pad_1727.2x1727.2_um 18 2540 -20320)\r
96 (pin Oval[A]Pad_1727.2x1727.2_um 17 0 -20320)\r
97 (pin Oval[A]Pad_1727.2x1727.2_um 16 2540 -17780)\r
98 (pin Oval[A]Pad_1727.2x1727.2_um 15 0 -17780)\r
99 (pin Oval[A]Pad_1727.2x1727.2_um 14 2540 -15240)\r
100 (pin Oval[A]Pad_1727.2x1727.2_um 13 0 -15240)\r
101 (pin Oval[A]Pad_1727.2x1727.2_um 12 2540 -12700)\r
102 (pin Oval[A]Pad_1727.2x1727.2_um 11 0 -12700)\r
103 (pin Oval[A]Pad_1727.2x1727.2_um 10 2540 -10160)\r
104 (pin Oval[A]Pad_1727.2x1727.2_um 9 0 -10160)\r
105 (pin Oval[A]Pad_1727.2x1727.2_um 8 2540 -7620)\r
106 (pin Oval[A]Pad_1727.2x1727.2_um 7 0 -7620)\r
107 (pin Oval[A]Pad_1727.2x1727.2_um 6 2540 -5080)\r
108 (pin Oval[A]Pad_1727.2x1727.2_um 5 0 -5080)\r
109 (pin Oval[A]Pad_1727.2x1727.2_um 4 2540 -2540)\r
110 (pin Oval[A]Pad_1727.2x1727.2_um 3 0 -2540)\r
111 (pin Oval[A]Pad_1727.2x1727.2_um 2 2540 0)\r
112 (pin Rect[A]Pad_1727.2x1727.2_um 1 0 0)\r
113 )\r
114 (image "DIP254P762X508-16N:DIP254P762X508-16N"\r
115 (outline (path signal 152.4 -6731 -965.2 -889 -965.2))\r
116 (outline (path signal 152.4 -889 18745.2 -3505.2 18745.2))\r
117 (outline (path signal 152.4 -3505.2 18745.2 -4114.8 18745.2))\r
118 (outline (path signal 152.4 -4114.8 18745.2 -6299.2 18745.2))\r
119 (outline (path signal 100 -7112 17221.2 -7112 18338.8))\r
120 (outline (path signal 100 -7112 18338.8 -8178.8 18338.8))\r
121 (outline (path signal 100 -8178.8 18338.8 -8178.8 17221.2))\r
122 (outline (path signal 100 -8178.8 17221.2 -7112 17221.2))\r
123 (outline (path signal 100 -7112 14681.2 -7112 15798.8))\r
124 (outline (path signal 100 -7112 15798.8 -8178.8 15798.8))\r
125 (outline (path signal 100 -8178.8 15798.8 -8178.8 14681.2))\r
126 (outline (path signal 100 -8178.8 14681.2 -7112 14681.2))\r
127 (outline (path signal 100 -7112 12141.2 -7112 13258.8))\r
128 (outline (path signal 100 -7112 13258.8 -8178.8 13258.8))\r
129 (outline (path signal 100 -8178.8 13258.8 -8178.8 12141.2))\r
130 (outline (path signal 100 -8178.8 12141.2 -7112 12141.2))\r
131 (outline (path signal 100 -7112 9601.2 -7112 10718.8))\r
132 (outline (path signal 100 -7112 10718.8 -8178.8 10718.8))\r
133 (outline (path signal 100 -8178.8 10718.8 -8178.8 9601.2))\r
134 (outline (path signal 100 -8178.8 9601.2 -7112 9601.2))\r
135 (outline (path signal 100 -7112 7061.2 -7112 8178.8))\r
136 (outline (path signal 100 -7112 8178.8 -8178.8 8178.8))\r
137 (outline (path signal 100 -8178.8 8178.8 -8178.8 7061.2))\r
138 (outline (path signal 100 -8178.8 7061.2 -7112 7061.2))\r
139 (outline (path signal 100 -7112 4521.2 -7112 5638.8))\r
140 (outline (path signal 100 -7112 5638.8 -8178.8 5638.8))\r
141 (outline (path signal 100 -8178.8 5638.8 -8178.8 4521.2))\r
142 (outline (path signal 100 -8178.8 4521.2 -7112 4521.2))\r
143 (outline (path signal 100 -7112 1981.2 -7112 3098.8))\r
144 (outline (path signal 100 -7112 3098.8 -8178.8 3098.8))\r
145 (outline (path signal 100 -8178.8 3098.8 -8178.8 1981.2))\r
146 (outline (path signal 100 -8178.8 1981.2 -7112 1981.2))\r
147 (outline (path signal 100 -7112 -558.8 -7112 558.8))\r
148 (outline (path signal 100 -7112 558.8 -8178.8 558.8))\r
149 (outline (path signal 100 -8178.8 558.8 -8178.8 -558.8))\r
150 (outline (path signal 100 -8178.8 -558.8 -7112 -558.8))\r
151 (outline (path signal 100 -508 558.8 -508 -558.8))\r
152 (outline (path signal 100 -508 -558.8 558.8 -558.8))\r
153 (outline (path signal 100 558.8 -558.8 558.8 558.8))\r
154 (outline (path signal 100 558.8 558.8 -508 558.8))\r
155 (outline (path signal 100 -508 3098.8 -508 1981.2))\r
156 (outline (path signal 100 -508 1981.2 558.8 1981.2))\r
157 (outline (path signal 100 558.8 1981.2 558.8 3098.8))\r
158 (outline (path signal 100 558.8 3098.8 -508 3098.8))\r
159 (outline (path signal 100 -508 5638.8 -508 4521.2))\r
160 (outline (path signal 100 -508 4521.2 558.8 4521.2))\r
161 (outline (path signal 100 558.8 4521.2 558.8 5638.8))\r
162 (outline (path signal 100 558.8 5638.8 -508 5638.8))\r
163 (outline (path signal 100 -508 8178.8 -508 7061.2))\r
164 (outline (path signal 100 -508 7061.2 558.8 7061.2))\r
165 (outline (path signal 100 558.8 7061.2 558.8 8178.8))\r
166 (outline (path signal 100 558.8 8178.8 -508 8178.8))\r
167 (outline (path signal 100 -508 10718.8 -508 9601.2))\r
168 (outline (path signal 100 -508 9601.2 558.8 9601.2))\r
169 (outline (path signal 100 558.8 9601.2 558.8 10718.8))\r
170 (outline (path signal 100 558.8 10718.8 -508 10718.8))\r
171 (outline (path signal 100 -508 13258.8 -508 12141.2))\r
172 (outline (path signal 100 -508 12141.2 558.8 12141.2))\r
173 (outline (path signal 100 558.8 12141.2 558.8 13258.8))\r
174 (outline (path signal 100 558.8 13258.8 -508 13258.8))\r
175 (outline (path signal 100 -508 15798.8 -508 14681.2))\r
176 (outline (path signal 100 -508 14681.2 558.8 14681.2))\r
177 (outline (path signal 100 558.8 14681.2 558.8 15798.8))\r
178 (outline (path signal 100 558.8 15798.8 -508 15798.8))\r
179 (outline (path signal 100 -508 18338.8 -508 17221.2))\r
180 (outline (path signal 100 -508 17221.2 558.8 17221.2))\r
181 (outline (path signal 100 558.8 17221.2 558.8 18338.8))\r
182 (outline (path signal 100 558.8 18338.8 -508 18338.8))\r
183 (outline (path signal 100 -7112 -965.2 -508 -965.2))\r
184 (outline (path signal 100 -508 -965.2 -508 18745.2))\r
185 (outline (path signal 100 -508 18745.2 -3505.2 18745.2))\r
186 (outline (path signal 100 -3505.2 18745.2 -4114.8 18745.2))\r
187 (outline (path signal 100 -4114.8 18745.2 -7112 18745.2))\r
188 (outline (path signal 100 -7112 18745.2 -7112 -965.2))\r
189 (pin Rect[A]Pad_1676.4x1676.4_um 1 -7620 17780)\r
190 (pin Round[A]Pad_1676.4_um 2 -7620 15240)\r
191 (pin Round[A]Pad_1676.4_um 3 -7620 12700)\r
192 (pin Round[A]Pad_1676.4_um 4 -7620 10160)\r
193 (pin Round[A]Pad_1676.4_um 5 -7620 7620)\r
194 (pin Round[A]Pad_1676.4_um 6 -7620 5080)\r
195 (pin Round[A]Pad_1676.4_um 7 -7620 2540)\r
196 (pin Round[A]Pad_1676.4_um 8 -7620 0)\r
197 (pin Round[A]Pad_1676.4_um 9 0 0)\r
198 (pin Round[A]Pad_1676.4_um 10 0 2540)\r
199 (pin Round[A]Pad_1676.4_um 11 0 5080)\r
200 (pin Round[A]Pad_1676.4_um 12 0 7620)\r
201 (pin Round[A]Pad_1676.4_um 13 0 10160)\r
202 (pin Round[A]Pad_1676.4_um 14 0 12700)\r
203 (pin Round[A]Pad_1676.4_um 15 0 15240)\r
204 (pin Round[A]Pad_1676.4_um 16 0 17780)\r
205 )\r
206 (image "DIP254P762X508-16N:DIP254P762X508-16N::1"\r
207 (outline (path signal 100 -7112 18745.2 -7112 -965.2))\r
208 (outline (path signal 100 -4114.8 18745.2 -7112 18745.2))\r
209 (outline (path signal 100 -3505.2 18745.2 -4114.8 18745.2))\r
210 (outline (path signal 100 -508 18745.2 -3505.2 18745.2))\r
211 (outline (path signal 100 -508 -965.2 -508 18745.2))\r
212 (outline (path signal 100 -7112 -965.2 -508 -965.2))\r
213 (outline (path signal 100 558.8 18338.8 -508 18338.8))\r
214 (outline (path signal 100 558.8 17221.2 558.8 18338.8))\r
215 (outline (path signal 100 -508 17221.2 558.8 17221.2))\r
216 (outline (path signal 100 -508 18338.8 -508 17221.2))\r
217 (outline (path signal 100 558.8 15798.8 -508 15798.8))\r
218 (outline (path signal 100 558.8 14681.2 558.8 15798.8))\r
219 (outline (path signal 100 -508 14681.2 558.8 14681.2))\r
220 (outline (path signal 100 -508 15798.8 -508 14681.2))\r
221 (outline (path signal 100 558.8 13258.8 -508 13258.8))\r
222 (outline (path signal 100 558.8 12141.2 558.8 13258.8))\r
223 (outline (path signal 100 -508 12141.2 558.8 12141.2))\r
224 (outline (path signal 100 -508 13258.8 -508 12141.2))\r
225 (outline (path signal 100 558.8 10718.8 -508 10718.8))\r
226 (outline (path signal 100 558.8 9601.2 558.8 10718.8))\r
227 (outline (path signal 100 -508 9601.2 558.8 9601.2))\r
228 (outline (path signal 100 -508 10718.8 -508 9601.2))\r
229 (outline (path signal 100 558.8 8178.8 -508 8178.8))\r
230 (outline (path signal 100 558.8 7061.2 558.8 8178.8))\r
231 (outline (path signal 100 -508 7061.2 558.8 7061.2))\r
232 (outline (path signal 100 -508 8178.8 -508 7061.2))\r
233 (outline (path signal 100 558.8 5638.8 -508 5638.8))\r
234 (outline (path signal 100 558.8 4521.2 558.8 5638.8))\r
235 (outline (path signal 100 -508 4521.2 558.8 4521.2))\r
236 (outline (path signal 100 -508 5638.8 -508 4521.2))\r
237 (outline (path signal 100 558.8 3098.8 -508 3098.8))\r
238 (outline (path signal 100 558.8 1981.2 558.8 3098.8))\r
239 (outline (path signal 100 -508 1981.2 558.8 1981.2))\r
240 (outline (path signal 100 -508 3098.8 -508 1981.2))\r
241 (outline (path signal 100 558.8 558.8 -508 558.8))\r
242 (outline (path signal 100 558.8 -558.8 558.8 558.8))\r
243 (outline (path signal 100 -508 -558.8 558.8 -558.8))\r
244 (outline (path signal 100 -508 558.8 -508 -558.8))\r
245 (outline (path signal 100 -8178.8 -558.8 -7112 -558.8))\r
246 (outline (path signal 100 -8178.8 558.8 -8178.8 -558.8))\r
247 (outline (path signal 100 -7112 558.8 -8178.8 558.8))\r
248 (outline (path signal 100 -7112 -558.8 -7112 558.8))\r
249 (outline (path signal 100 -8178.8 1981.2 -7112 1981.2))\r
250 (outline (path signal 100 -8178.8 3098.8 -8178.8 1981.2))\r
251 (outline (path signal 100 -7112 3098.8 -8178.8 3098.8))\r
252 (outline (path signal 100 -7112 1981.2 -7112 3098.8))\r
253 (outline (path signal 100 -8178.8 4521.2 -7112 4521.2))\r
254 (outline (path signal 100 -8178.8 5638.8 -8178.8 4521.2))\r
255 (outline (path signal 100 -7112 5638.8 -8178.8 5638.8))\r
256 (outline (path signal 100 -7112 4521.2 -7112 5638.8))\r
257 (outline (path signal 100 -8178.8 7061.2 -7112 7061.2))\r
258 (outline (path signal 100 -8178.8 8178.8 -8178.8 7061.2))\r
259 (outline (path signal 100 -7112 8178.8 -8178.8 8178.8))\r
260 (outline (path signal 100 -7112 7061.2 -7112 8178.8))\r
261 (outline (path signal 100 -8178.8 9601.2 -7112 9601.2))\r
262 (outline (path signal 100 -8178.8 10718.8 -8178.8 9601.2))\r
263 (outline (path signal 100 -7112 10718.8 -8178.8 10718.8))\r
264 (outline (path signal 100 -7112 9601.2 -7112 10718.8))\r
265 (outline (path signal 100 -8178.8 12141.2 -7112 12141.2))\r
266 (outline (path signal 100 -8178.8 13258.8 -8178.8 12141.2))\r
267 (outline (path signal 100 -7112 13258.8 -8178.8 13258.8))\r
268 (outline (path signal 100 -7112 12141.2 -7112 13258.8))\r
269 (outline (path signal 100 -8178.8 14681.2 -7112 14681.2))\r
270 (outline (path signal 100 -8178.8 15798.8 -8178.8 14681.2))\r
271 (outline (path signal 100 -7112 15798.8 -8178.8 15798.8))\r
272 (outline (path signal 100 -7112 14681.2 -7112 15798.8))\r
273 (outline (path signal 100 -8178.8 17221.2 -7112 17221.2))\r
274 (outline (path signal 100 -8178.8 18338.8 -8178.8 17221.2))\r
275 (outline (path signal 100 -7112 18338.8 -8178.8 18338.8))\r
276 (outline (path signal 100 -7112 17221.2 -7112 18338.8))\r
277 (outline (path signal 152.4 -4114.8 18745.2 -6299.2 18745.2))\r
278 (outline (path signal 152.4 -3505.2 18745.2 -4114.8 18745.2))\r
279 (outline (path signal 152.4 -889 18745.2 -3505.2 18745.2))\r
280 (outline (path signal 152.4 -6731 -965.2 -889 -965.2))\r
281 (pin Round[A]Pad_1676.4_um 16 0 17780)\r
282 (pin Round[A]Pad_1676.4_um 15 0 15240)\r
283 (pin Round[A]Pad_1676.4_um 14 0 12700)\r
284 (pin Round[A]Pad_1676.4_um 13 0 10160)\r
285 (pin Round[A]Pad_1676.4_um 12 0 7620)\r
286 (pin Round[A]Pad_1676.4_um 11 0 5080)\r
287 (pin Round[A]Pad_1676.4_um 10 0 2540)\r
288 (pin Round[A]Pad_1676.4_um 9 0 0)\r
289 (pin Round[A]Pad_1676.4_um 8 -7620 0)\r
290 (pin Round[A]Pad_1676.4_um 7 -7620 2540)\r
291 (pin Round[A]Pad_1676.4_um 6 -7620 5080)\r
292 (pin Round[A]Pad_1676.4_um 5 -7620 7620)\r
293 (pin Round[A]Pad_1676.4_um 4 -7620 10160)\r
294 (pin Round[A]Pad_1676.4_um 3 -7620 12700)\r
295 (pin Round[A]Pad_1676.4_um 2 -7620 15240)\r
296 (pin Rect[A]Pad_1676.4x1676.4_um 1 -7620 17780)\r
297 )\r
298 (image "SN74HC166N:DIP254P762X508-16"\r
299 (outline (path signal 152.4 -6731 -965.2 -889 -965.2))\r
300 (outline (path signal 152.4 -889 18745.2 -3505.2 18745.2))\r
301 (outline (path signal 152.4 -3505.2 18745.2 -4114.8 18745.2))\r
302 (outline (path signal 152.4 -4114.8 18745.2 -6299.2 18745.2))\r
303 (outline (path signal 152.4 -7112 17221.2 -7112 18338.8))\r
304 (outline (path signal 152.4 -7112 18338.8 -8178.8 18338.8))\r
305 (outline (path signal 152.4 -8178.8 18338.8 -8178.8 17221.2))\r
306 (outline (path signal 152.4 -8178.8 17221.2 -7112 17221.2))\r
307 (outline (path signal 152.4 -7112 14681.2 -7112 15798.8))\r
308 (outline (path signal 152.4 -7112 15798.8 -8178.8 15798.8))\r
309 (outline (path signal 152.4 -8178.8 15798.8 -8178.8 14681.2))\r
310 (outline (path signal 152.4 -8178.8 14681.2 -7112 14681.2))\r
311 (outline (path signal 152.4 -7112 12141.2 -7112 13258.8))\r
312 (outline (path signal 152.4 -7112 13258.8 -8178.8 13258.8))\r
313 (outline (path signal 152.4 -8178.8 13258.8 -8178.8 12141.2))\r
314 (outline (path signal 152.4 -8178.8 12141.2 -7112 12141.2))\r
315 (outline (path signal 152.4 -7112 9601.2 -7112 10718.8))\r
316 (outline (path signal 152.4 -7112 10718.8 -8178.8 10718.8))\r
317 (outline (path signal 152.4 -8178.8 10718.8 -8178.8 9601.2))\r
318 (outline (path signal 152.4 -8178.8 9601.2 -7112 9601.2))\r
319 (outline (path signal 152.4 -7112 7061.2 -7112 8178.8))\r
320 (outline (path signal 152.4 -7112 8178.8 -8178.8 8178.8))\r
321 (outline (path signal 152.4 -8178.8 8178.8 -8178.8 7061.2))\r
322 (outline (path signal 152.4 -8178.8 7061.2 -7112 7061.2))\r
323 (outline (path signal 152.4 -7112 4521.2 -7112 5638.8))\r
324 (outline (path signal 152.4 -7112 5638.8 -8178.8 5638.8))\r
325 (outline (path signal 152.4 -8178.8 5638.8 -8178.8 4521.2))\r
326 (outline (path signal 152.4 -8178.8 4521.2 -7112 4521.2))\r
327 (outline (path signal 152.4 -7112 1981.2 -7112 3098.8))\r
328 (outline (path signal 152.4 -7112 3098.8 -8178.8 3098.8))\r
329 (outline (path signal 152.4 -8178.8 3098.8 -8178.8 1981.2))\r
330 (outline (path signal 152.4 -8178.8 1981.2 -7112 1981.2))\r
331 (outline (path signal 152.4 -7112 -558.8 -7112 558.8))\r
332 (outline (path signal 152.4 -7112 558.8 -8178.8 558.8))\r
333 (outline (path signal 152.4 -8178.8 558.8 -8178.8 -558.8))\r
334 (outline (path signal 152.4 -8178.8 -558.8 -7112 -558.8))\r
335 (outline (path signal 152.4 -508 558.8 -508 -558.8))\r
336 (outline (path signal 152.4 -508 -558.8 558.8 -558.8))\r
337 (outline (path signal 152.4 558.8 -558.8 558.8 558.8))\r
338 (outline (path signal 152.4 558.8 558.8 -508 558.8))\r
339 (outline (path signal 152.4 -508 3098.8 -508 1981.2))\r
340 (outline (path signal 152.4 -508 1981.2 558.8 1981.2))\r
341 (outline (path signal 152.4 558.8 1981.2 558.8 3098.8))\r
342 (outline (path signal 152.4 558.8 3098.8 -508 3098.8))\r
343 (outline (path signal 152.4 -508 5638.8 -508 4521.2))\r
344 (outline (path signal 152.4 -508 4521.2 558.8 4521.2))\r
345 (outline (path signal 152.4 558.8 4521.2 558.8 5638.8))\r
346 (outline (path signal 152.4 558.8 5638.8 -508 5638.8))\r
347 (outline (path signal 152.4 -508 8178.8 -508 7061.2))\r
348 (outline (path signal 152.4 -508 7061.2 558.8 7061.2))\r
349 (outline (path signal 152.4 558.8 7061.2 558.8 8178.8))\r
350 (outline (path signal 152.4 558.8 8178.8 -508 8178.8))\r
351 (outline (path signal 152.4 -508 10718.8 -508 9601.2))\r
352 (outline (path signal 152.4 -508 9601.2 558.8 9601.2))\r
353 (outline (path signal 152.4 558.8 9601.2 558.8 10718.8))\r
354 (outline (path signal 152.4 558.8 10718.8 -508 10718.8))\r
355 (outline (path signal 152.4 -508 13258.8 -508 12141.2))\r
356 (outline (path signal 152.4 -508 12141.2 558.8 12141.2))\r
357 (outline (path signal 152.4 558.8 12141.2 558.8 13258.8))\r
358 (outline (path signal 152.4 558.8 13258.8 -508 13258.8))\r
359 (outline (path signal 152.4 -508 15798.8 -508 14681.2))\r
360 (outline (path signal 152.4 -508 14681.2 558.8 14681.2))\r
361 (outline (path signal 152.4 558.8 14681.2 558.8 15798.8))\r
362 (outline (path signal 152.4 558.8 15798.8 -508 15798.8))\r
363 (outline (path signal 152.4 -508 18338.8 -508 17221.2))\r
364 (outline (path signal 152.4 -508 17221.2 558.8 17221.2))\r
365 (outline (path signal 152.4 558.8 17221.2 558.8 18338.8))\r
366 (outline (path signal 152.4 558.8 18338.8 -508 18338.8))\r
367 (outline (path signal 152.4 -7112 -965.2 -508 -965.2))\r
368 (outline (path signal 152.4 -508 -965.2 -508 18745.2))\r
369 (outline (path signal 152.4 -508 18745.2 -3505.2 18745.2))\r
370 (outline (path signal 152.4 -3505.2 18745.2 -4114.8 18745.2))\r
371 (outline (path signal 152.4 -4114.8 18745.2 -7112 18745.2))\r
372 (outline (path signal 152.4 -7112 18745.2 -7112 -965.2))\r
373 (pin Rect[A]Pad_1676.4x1676.4_um 1 -7620 17780)\r
374 (pin Round[A]Pad_1676.4_um 2 -7620 15240)\r
375 (pin Round[A]Pad_1676.4_um 3 -7620 12700)\r
376 (pin Round[A]Pad_1676.4_um 4 -7620 10160)\r
377 (pin Round[A]Pad_1676.4_um 5 -7620 7620)\r
378 (pin Round[A]Pad_1676.4_um 6 -7620 5080)\r
379 (pin Round[A]Pad_1676.4_um 7 -7620 2540)\r
380 (pin Round[A]Pad_1676.4_um 8 -7620 0)\r
381 (pin Round[A]Pad_1676.4_um 9 0 0)\r
382 (pin Round[A]Pad_1676.4_um 10 0 2540)\r
383 (pin Round[A]Pad_1676.4_um 11 0 5080)\r
384 (pin Round[A]Pad_1676.4_um 12 0 7620)\r
385 (pin Round[A]Pad_1676.4_um 13 0 10160)\r
386 (pin Round[A]Pad_1676.4_um 14 0 12700)\r
387 (pin Round[A]Pad_1676.4_um 15 0 15240)\r
388 (pin Round[A]Pad_1676.4_um 16 0 17780)\r
389 )\r
390 (image "digikey-footprints:PinHeader_2x6_P2.54mm_Vertical_SMD"\r
391 (outline (path signal 50 -7850 4325 7875 4325))\r
392 (outline (path signal 50 -7850 -4325 -7850 4325))\r
393 (outline (path signal 50 7875 4275 7875 -4325))\r
394 (outline (path signal 50 -7850 -4325 7850 -4325))\r
395 (outline (path signal 100 -7200 -3600 -7700 -3600))\r
396 (outline (path signal 100 -7700 -3600 -7700 -2200))\r
397 (outline (path signal 100 7200 -3600 7700 -3600))\r
398 (outline (path signal 100 7700 -3600 7700 -2500))\r
399 (outline (path signal 100 7200 3600 7700 3600))\r
400 (outline (path signal 100 7700 3600 7700 2400))\r
401 (outline (path signal 100 -7700 2200 -7700 2700))\r
402 (outline (path signal 100 -7700 2700 -7100 3300))\r
403 (outline (path signal 100 -7100 3300 -7100 3500))\r
404 (outline (path signal 100 -7625 -3500 -7600 2600))\r
405 (outline (path signal 100 7600 3500 -6700 3500))\r
406 (outline (path signal 100 -6700 3500 -7600 2600))\r
407 (outline (path signal 100 7620 3500 7620 -3500))\r
408 (outline (path signal 100 -7620 -3500 7620 -3500))\r
409 (pin Rect[T]Pad_1280x3680_um 1 -6350 2220)\r
410 (pin Rect[T]Pad_1280x3680_um 2 -3810 2220)\r
411 (pin Rect[T]Pad_1280x3680_um 3 -1270 2220)\r
412 (pin Rect[T]Pad_1280x3680_um 4 1270 2220)\r
413 (pin Rect[T]Pad_1280x3680_um 5 3810 2220)\r
414 (pin Rect[T]Pad_1280x3680_um 6 6350 2220)\r
415 (pin Rect[T]Pad_1280x3680_um 7 -6350 -2220)\r
416 (pin Rect[T]Pad_1280x3680_um 8 -3810 -2220)\r
417 (pin Rect[T]Pad_1280x3680_um 9 -1270 -2220)\r
418 (pin Rect[T]Pad_1280x3680_um 10 1270 -2220)\r
419 (pin Rect[T]Pad_1280x3680_um 11 3810 -2220)\r
420 (pin Rect[T]Pad_1280x3680_um 12 6350 -2220)\r
421 )\r
422 (padstack Round[A]Pad_1676.4_um\r
423 (shape (circle F.Cu 1676.4))\r
424 (shape (circle B.Cu 1676.4))\r
425 (attach off)\r
426 )\r
427 (padstack Oval[A]Pad_1727.2x1727.2_um\r
428 (shape (path F.Cu 1727.2 0 0 0 0))\r
429 (shape (path B.Cu 1727.2 0 0 0 0))\r
430 (attach off)\r
431 )\r
432 (padstack Rect[T]Pad_1280x3680_um\r
433 (shape (rect F.Cu -640 -1840 640 1840))\r
434 (attach off)\r
435 )\r
436 (padstack Rect[A]Pad_1676.4x1676.4_um\r
437 (shape (rect F.Cu -838.2 -838.2 838.2 838.2))\r
438 (shape (rect B.Cu -838.2 -838.2 838.2 838.2))\r
439 (attach off)\r
440 )\r
441 (padstack Rect[A]Pad_1727.2x1727.2_um\r
442 (shape (rect F.Cu -863.6 -863.6 863.6 863.6))\r
443 (shape (rect B.Cu -863.6 -863.6 863.6 863.6))\r
444 (attach off)\r
445 )\r
446 (padstack "Via[0-1]_600:400_um"\r
447 (shape (circle F.Cu 600))\r
448 (shape (circle B.Cu 600))\r
449 (attach off)\r
450 )\r
451 )\r
452 (network\r
453 (net "Net-(P8-Pad3)"\r
454 (pins P8-3)\r
455 )\r
456 (net "Net-(P8-Pad6)"\r
457 (pins P8-6)\r
458 )\r
459 (net "Net-(P8-Pad7)"\r
460 (pins P8-7)\r
461 )\r
462 (net "Net-(P8-Pad8)"\r
463 (pins P8-8)\r
464 )\r
465 (net "Net-(P8-Pad9)"\r
466 (pins P8-9)\r
467 )\r
468 (net "Net-(P8-Pad10)"\r
469 (pins P8-10)\r
470 )\r
471 (net "Net-(P8-Pad12)"\r
472 (pins P8-12)\r
473 )\r
474 (net "Net-(P8-Pad13)"\r
475 (pins P8-13)\r
476 )\r
477 (net "Net-(P8-Pad14)"\r
478 (pins P8-14)\r
479 )\r
480 (net "Net-(P8-Pad16)"\r
481 (pins P8-16)\r
482 )\r
483 (net "Net-(P8-Pad18)"\r
484 (pins P8-18)\r
485 )\r
486 (net "Net-(P8-Pad19)"\r
487 (pins P8-19)\r
488 )\r
489 (net "Net-(P8-Pad20)"\r
490 (pins P8-20)\r
491 )\r
492 (net "Net-(P8-Pad21)"\r
493 (pins P8-21)\r
494 )\r
495 (net "Net-(P8-Pad22)"\r
496 (pins P8-22)\r
497 )\r
498 (net "Net-(P8-Pad23)"\r
499 (pins P8-23)\r
500 )\r
501 (net "Net-(P8-Pad24)"\r
502 (pins P8-24)\r
503 )\r
504 (net "Net-(P8-Pad25)"\r
505 (pins P8-25)\r
506 )\r
507 (net "Net-(P8-Pad26)"\r
508 (pins P8-26)\r
509 )\r
510 (net "Net-(P8-Pad27)"\r
511 (pins P8-27)\r
512 )\r
513 (net "Net-(P8-Pad28)"\r
514 (pins P8-28)\r
515 )\r
516 (net "Net-(P8-Pad29)"\r
517 (pins P8-29)\r
518 )\r
519 (net "Net-(P8-Pad30)"\r
520 (pins P8-30)\r
521 )\r
522 (net "Net-(P8-Pad31)"\r
523 (pins P8-31)\r
524 )\r
525 (net "Net-(P8-Pad32)"\r
526 (pins P8-32)\r
527 )\r
528 (net "Net-(P8-Pad33)"\r
529 (pins P8-33)\r
530 )\r
531 (net "Net-(P8-Pad34)"\r
532 (pins P8-34)\r
533 )\r
534 (net "Net-(P8-Pad35)"\r
535 (pins P8-35)\r
536 )\r
537 (net "Net-(P8-Pad36)"\r
538 (pins P8-36)\r
539 )\r
540 (net "Net-(P8-Pad37)"\r
541 (pins P8-37)\r
542 )\r
543 (net "Net-(P8-Pad38)"\r
544 (pins P8-38)\r
545 )\r
546 (net "Net-(P8-Pad39)"\r
547 (pins P8-39)\r
548 )\r
549 (net "Net-(P8-Pad40)"\r
550 (pins P8-40)\r
551 )\r
552 (net "Net-(P8-Pad41)"\r
553 (pins P8-41)\r
554 )\r
555 (net "Net-(P8-Pad42)"\r
556 (pins P8-42)\r
557 )\r
558 (net "Net-(P8-Pad43)"\r
559 (pins P8-43)\r
560 )\r
561 (net "Net-(P8-Pad44)"\r
562 (pins P8-44)\r
563 )\r
564 (net "Net-(P8-Pad45)"\r
565 (pins P8-45)\r
566 )\r
567 (net "Net-(P8-Pad46)"\r
568 (pins P8-46)\r
569 )\r
570 (net "Net-(P9-Pad11)"\r
571 (pins P9-11)\r
572 )\r
573 (net "Net-(P9-Pad12)"\r
574 (pins P9-12)\r
575 )\r
576 (net "Net-(P9-Pad13)"\r
577 (pins P9-13)\r
578 )\r
579 (net "Net-(P9-Pad14)"\r
580 (pins P9-14)\r
581 )\r
582 (net "Net-(P9-Pad15)"\r
583 (pins P9-15)\r
584 )\r
585 (net "Net-(P9-Pad16)"\r
586 (pins P9-16)\r
587 )\r
588 (net "Net-(P9-Pad17)"\r
589 (pins P9-17)\r
590 )\r
591 (net "Net-(P9-Pad18)"\r
592 (pins P9-18)\r
593 )\r
594 (net "Net-(P9-Pad19)"\r
595 (pins P9-19)\r
596 )\r
597 (net "Net-(P9-Pad20)"\r
598 (pins P9-20)\r
599 )\r
600 (net "Net-(P9-Pad21)"\r
601 (pins P9-21)\r
602 )\r
603 (net "Net-(P9-Pad22)"\r
604 (pins P9-22)\r
605 )\r
606 (net "Net-(P9-Pad23)"\r
607 (pins P9-23)\r
608 )\r
609 (net "Net-(P9-Pad24)"\r
610 (pins P9-24)\r
611 )\r
612 (net "Net-(P9-Pad25)"\r
613 (pins P9-25)\r
614 )\r
615 (net "Net-(P9-Pad26)"\r
616 (pins P9-26)\r
617 )\r
618 (net "Net-(P9-Pad27)"\r
619 (pins P9-27)\r
620 )\r
621 (net "Net-(P9-Pad28)"\r
622 (pins P9-28)\r
623 )\r
624 (net "Net-(P9-Pad29)"\r
625 (pins P9-29)\r
626 )\r
627 (net "Net-(P9-Pad30)"\r
628 (pins P9-30)\r
629 )\r
630 (net "Net-(P9-Pad31)"\r
631 (pins P9-31)\r
632 )\r
633 (net "Net-(P9-Pad33)"\r
634 (pins P9-33)\r
635 )\r
636 (net "Net-(P9-Pad35)"\r
637 (pins P9-35)\r
638 )\r
639 (net "Net-(P9-Pad36)"\r
640 (pins P9-36)\r
641 )\r
642 (net "Net-(P9-Pad37)"\r
643 (pins P9-37)\r
644 )\r
645 (net "Net-(P9-Pad38)"\r
646 (pins P9-38)\r
647 )\r
648 (net "Net-(P9-Pad39)"\r
649 (pins P9-39)\r
650 )\r
651 (net "Net-(P9-Pad40)"\r
652 (pins P9-40)\r
653 )\r
654 (net "Net-(P9-Pad41)"\r
655 (pins P9-41)\r
656 )\r
657 (net "Net-(P9-Pad42)"\r
658 (pins P9-42)\r
659 )\r
660 (net PWR_BUT\r
661 (pins P9-9)\r
662 )\r
663 (net SYS_RESETN\r
664 (pins P9-10)\r
665 )\r
666 (net VDD_ADC\r
667 (pins P9-32)\r
668 )\r
669 (net GNDA_ADC\r
670 (pins P9-34)\r
671 )\r
672 (net "Net-(U1-Pad4)"\r
673 (pins U1-4)\r
674 )\r
675 (net "Net-(U1-Pad5)"\r
676 (pins U1-5)\r
677 )\r
678 (net "Net-(U1-Pad6)"\r
679 (pins U1-6)\r
680 )\r
681 (net "Net-(U1-Pad7)"\r
682 (pins U1-7)\r
683 )\r
684 (net "Net-(U1-Pad9)"\r
685 (pins U1-9)\r
686 )\r
687 (net "Net-(U1-Pad10)"\r
688 (pins U1-10)\r
689 )\r
690 (net "Net-(U1-Pad11)"\r
691 (pins U1-11)\r
692 )\r
693 (net "Net-(U1-Pad12)"\r
694 (pins U1-12)\r
695 )\r
696 (net "Net-(U1-Pad14)"\r
697 (pins U1-14)\r
698 )\r
699 (net "Net-(U1-Pad15)"\r
700 (pins U1-15)\r
701 )\r
702 (net "Net-(U2-Pad15)"\r
703 (pins U2-15)\r
704 )\r
705 (net "Net-(U2-Pad14)"\r
706 (pins U2-14)\r
707 )\r
708 (net "Net-(U2-Pad12)"\r
709 (pins U2-12)\r
710 )\r
711 (net "Net-(U2-Pad11)"\r
712 (pins U2-11)\r
713 )\r
714 (net /d1\r
715 (pins J1-1)\r
716 )\r
717 (net /d2\r
718 (pins J1-2)\r
719 )\r
720 (net /d3\r
721 (pins J1-3)\r
722 )\r
723 (net /d4\r
724 (pins J1-4)\r
725 )\r
726 (net /d5\r
727 (pins J1-5)\r
728 )\r
729 (net /d6\r
730 (pins J1-6)\r
731 )\r
732 (net /d7\r
733 (pins J1-7)\r
734 )\r
735 (net /d8\r
736 (pins J1-8)\r
737 )\r
738 (net "Net-(J1-Pad9)"\r
739 (pins J1-9)\r
740 )\r
741 (net "Net-(J1-Pad10)"\r
742 (pins J1-10)\r
743 )\r
744 (net "Net-(J1-Pad11)"\r
745 (pins J1-11)\r
746 )\r
747 (net "Net-(J1-Pad12)"\r
748 (pins J1-12)\r
749 )\r
750 (net SR1_CLR\r
751 (pins P8-17 U2-9)\r
752 )\r
753 (net SR1_SHLD\r
754 (pins P8-15 U2-7)\r
755 )\r
756 (net SR1_CLK\r
757 (pins P8-11 U2-3)\r
758 )\r
759 (net SR1_CLKINH\r
760 (pins P8-5 U2-5)\r
761 )\r
762 (net SR1_QH_T\r
763 (pins P8-4 U1-2)\r
764 )\r
765 (net PGND\r
766 (pins P8-2 P8-1 P9-46 P9-45 P9-44 P9-43 P9-2 P9-1 U1-8 U1-13 U2-13 U2-8 U3-1\r
767 U3-8)\r
768 )\r
769 (net 5v\r
770 (pins P9-8 P9-7 P9-6 P9-5 U1-1 U2-16 U3-16)\r
771 )\r
772 (net BB3.3\r
773 (pins P9-4 P9-3 U1-16 U2-1)\r
774 )\r
775 (net SR1_QH\r
776 (pins U1-3 U3-13)\r
777 )\r
778 (net SR1_CLR_T\r
779 (pins U2-10 U3-9)\r
780 )\r
781 (net SR1_SHLD_T\r
782 (pins U2-6 U3-15)\r
783 )\r
784 (net SR1_CLKINH_T\r
785 (pins U2-4 U3-6)\r
786 )\r
787 (net SR1_CLK_T\r
788 (pins U2-2 U3-7)\r
789 )\r
790 (net /p8\r
791 (pins U3-14)\r
792 )\r
793 (net /p7\r
794 (pins U3-12)\r
795 )\r
796 (net /p6\r
797 (pins U3-11)\r
798 )\r
799 (net /p5\r
800 (pins U3-10)\r
801 )\r
802 (net /p4\r
803 (pins U3-5)\r
804 )\r
805 (net /p3\r
806 (pins U3-4)\r
807 )\r
808 (net /p2\r
809 (pins U3-3)\r
810 )\r
811 (net /p1\r
812 (pins U3-2)\r
813 )\r
814 (class kicad_default "" +3V3 +5V /GPIO0_27_SR_CLR /GPIO1_13_SR_CLK /GPIO1_15_SR_SHLD\r
815 /GPIO1_2_SR_CLKINH /GPIO1_7_SR_QH /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /p1\r
816 /p2 /p3 /p4 /p5 /p6 /p7 /p8 5v BB3.3 GNDA_ADC GNDD "Net-(J1-Pad10)"\r
817 "Net-(J1-Pad11)" "Net-(J1-Pad12)" "Net-(J1-Pad9)" "Net-(P8-Pad10)" "Net-(P8-Pad12)"\r
818 "Net-(P8-Pad13)" "Net-(P8-Pad14)" "Net-(P8-Pad16)" "Net-(P8-Pad18)"\r
819 "Net-(P8-Pad19)" "Net-(P8-Pad20)" "Net-(P8-Pad21)" "Net-(P8-Pad22)"\r
820 "Net-(P8-Pad23)" "Net-(P8-Pad24)" "Net-(P8-Pad25)" "Net-(P8-Pad26)"\r
821 "Net-(P8-Pad27)" "Net-(P8-Pad28)" "Net-(P8-Pad29)" "Net-(P8-Pad3)" "Net-(P8-Pad30)"\r
822 "Net-(P8-Pad31)" "Net-(P8-Pad32)" "Net-(P8-Pad33)" "Net-(P8-Pad34)"\r
823 "Net-(P8-Pad35)" "Net-(P8-Pad36)" "Net-(P8-Pad37)" "Net-(P8-Pad38)"\r
824 "Net-(P8-Pad39)" "Net-(P8-Pad40)" "Net-(P8-Pad41)" "Net-(P8-Pad42)"\r
825 "Net-(P8-Pad43)" "Net-(P8-Pad44)" "Net-(P8-Pad45)" "Net-(P8-Pad46)"\r
826 "Net-(P8-Pad6)" "Net-(P8-Pad7)" "Net-(P8-Pad8)" "Net-(P8-Pad9)" "Net-(P9-Pad11)"\r
827 "Net-(P9-Pad12)" "Net-(P9-Pad13)" "Net-(P9-Pad14)" "Net-(P9-Pad15)"\r
828 "Net-(P9-Pad16)" "Net-(P9-Pad17)" "Net-(P9-Pad18)" "Net-(P9-Pad19)"\r
829 "Net-(P9-Pad20)" "Net-(P9-Pad21)" "Net-(P9-Pad22)" "Net-(P9-Pad23)"\r
830 "Net-(P9-Pad24)" "Net-(P9-Pad25)" "Net-(P9-Pad26)" "Net-(P9-Pad27)"\r
831 "Net-(P9-Pad28)" "Net-(P9-Pad29)" "Net-(P9-Pad30)" "Net-(P9-Pad31)"\r
832 "Net-(P9-Pad33)" "Net-(P9-Pad35)" "Net-(P9-Pad36)" "Net-(P9-Pad37)"\r
833 "Net-(P9-Pad38)" "Net-(P9-Pad39)" "Net-(P9-Pad40)" "Net-(P9-Pad41)"\r
834 "Net-(P9-Pad42)" "Net-(U1-Pad10)" "Net-(U1-Pad11)" "Net-(U1-Pad12)"\r
835 "Net-(U1-Pad14)" "Net-(U1-Pad15)" "Net-(U1-Pad3)" "Net-(U1-Pad4)" "Net-(U1-Pad5)"\r
836 "Net-(U1-Pad6)" "Net-(U1-Pad7)" "Net-(U1-Pad9)" "Net-(U2-Pad10)" "Net-(U2-Pad11)"\r
837 "Net-(U2-Pad12)" "Net-(U2-Pad14)" "Net-(U2-Pad15)" "Net-(U2-Pad2)" "Net-(U2-Pad4)"\r
838 "Net-(U2-Pad6)" "Net-(U3-Pad10)" "Net-(U3-Pad11)" "Net-(U3-Pad12)" "Net-(U3-Pad14)"\r
839 "Net-(U3-Pad2)" "Net-(U3-Pad3)" "Net-(U3-Pad4)" "Net-(U3-Pad5)" PGND\r
840 PWR_BUT SR1_CLK SR1_CLKINH SR1_CLKINH_T SR1_CLK_T SR1_CLR SR1_CLR_T\r
841 SR1_QH SR1_QH_T SR1_SHLD SR1_SHLD_T SYS_RESETN VDD_ADC\r
842 (circuit\r
843 (use_via Via[0-1]_600:400_um)\r
844 )\r
845 (rule\r
846 (width 250)\r
847 (clearance 200.1)\r
848 )\r
849 )\r
850 )\r
851 (wiring\r
852 (wire (path B.Cu 250 115100 -36982.4 116264 -38146 131716 -38146 132880 -36982.4)(net 5v)(type protect))\r
853 (wire (path B.Cu 250 107480 -49682.4 111290 -45872.4 123990 -45872.4 125260 -44602.4)(net SR1_CLKINH_T)(type protect))\r
854 )\r
855)\r