fuck
[bort-segs.git] / bort-segs.pro
index 152769cb7209ca4e1fc17e8154dad5ded6b9d8e4..62d2759fa68aeef510339c06c9b154cd5a26444e 100644 (file)
@@ -1,33 +1,43 @@
-update=22/05/2015 07:44:53
-version=1
-last_client=kicad
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=
-[eeschema/libraries]
+update=1/11/2019 7:41:40 AM\r
+version=1\r
+last_client=kicad\r
+[general]\r
+version=1\r
+RootSch=\r
+BoardNm=\r
+[pcbnew]\r
+version=1\r
+LastNetListRead=\r
+UseCmpFile=1\r
+PadDrill=0.600000000000\r
+PadDrillOvalY=0.600000000000\r
+PadSizeH=1.500000000000\r
+PadSizeV=1.500000000000\r
+PcbTextSizeV=1.500000000000\r
+PcbTextSizeH=1.500000000000\r
+PcbTextThickness=0.300000000000\r
+ModuleTextSizeV=1.000000000000\r
+ModuleTextSizeH=1.000000000000\r
+ModuleTextSizeThickness=0.150000000000\r
+SolderMaskClearance=0.000000000000\r
+SolderMaskMinWidth=0.000000000000\r
+DrawSegmentWidth=0.200000000000\r
+BoardOutlineThickness=0.100000000000\r
+ModuleOutlineThickness=0.150000000000\r
+[cvpcb]\r
+version=1\r
+NetIExt=net\r
+[eeschema]\r
+version=1\r
+LibDir=\r
+[eeschema/libraries]\r
+[schematic_editor]\r
+version=1\r
+PageLayoutDescrFile=\r
+PlotDirectoryName=\r
+SubpartIdSeparator=0\r
+SubpartFirstId=65\r
+NetFmtName=Pcbnew\r
+SpiceAjustPassiveValues=0\r
+LabSize=50\r
+ERC_TestSimilarLabels=1\r