From: Ian Sutton Date: Fri, 11 Jan 2019 13:42:45 +0000 (-0600) Subject: fuck X-Git-Url: https://uglyman.kremlin.cc/gitweb/gitweb.cgi?p=bort-segs.git;a=commitdiff_plain;h=refs%2Fheads%2Fmaster;ds=sidebyside fuck --- diff --git a/bort-segs.dsn b/bort-segs.dsn new file mode 100644 index 0000000..fef966b --- /dev/null +++ b/bort-segs.dsn @@ -0,0 +1,1488 @@ +(pcb "C:\Users\kremlin\kicad\projects\bort-segs\bort-segs.dsn" + (parser + (string_quote ") + (space_in_quoted_tokens on) + (host_cad "KiCad's Pcbnew") + (host_version "(5.0.1)-3") + ) + (resolution um 10) + (unit um) + (structure + (layer F.Cu + (type signal) + (property + (index 0) + ) + ) + (layer B.Cu + (type signal) + (property + (index 1) + ) + ) + (boundary + (path pcb 0 400304 -126492 305816 -220980 30734 -220980 30734 -26924 + 400304 -26924 400304 -126492) + ) + (via "Via[0-1]_800:400_um") + (rule + (width 250) + (clearance 200.1) + (clearance 200.1 (type default_smd)) + (clearance 50 (type smd_smd)) + ) + ) + (placement + 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U8-11) + ) + (net "/Seg Logic/SS6_1" + (pins DSP6-7 U8-10) + ) + (net "/Seg Logic/SS6_4" + (pins DSP6-3 U8-9) + ) + (net "/Seg Logic/SS6_7" + (pins DSP6-10 U8-7) + ) + (net "/Seg Logic/SS6_6" + (pins DSP6-9 U8-6) + ) + (net "Net-(U8-Pad5)" + (pins U8-5) + ) + (net "Net-(U8-Pad4)" + (pins U8-4) + ) + (net "/Seg Logic/SEGCLK_6" + (pins U2-9 U8-1) + ) + (net "/Seg Logic/SEGCLK_5" + (pins U2-10 U7-1) + ) + (net "Net-(U7-Pad4)" + (pins U7-4) + ) + (net "Net-(U7-Pad5)" + (pins U7-5) + ) + (net "/Seg Logic/SS5_6" + (pins DSP5-9 U7-6) + ) + (net "/Seg Logic/SS5_7" + (pins DSP5-10 U7-7) + ) + (net "/Seg Logic/SS5_4" + (pins DSP5-3 U7-9) + ) + (net "/Seg Logic/SS5_1" + (pins DSP5-7 U7-10) + ) + (net "/Seg Logic/SS5_5" + (pins DSP5-2 U7-11) + ) + (net "/Seg Logic/SS5_2" + (pins DSP5-6 U7-12) + ) + (net "/Seg Logic/SS5_3" + (pins DSP5-4 U7-13) + ) + (net "Net-(U7-Pad14)" + (pins U7-14) + ) + (net "Net-(U6-Pad14)" + (pins U6-14) + ) + (net "/Seg Logic/SS4_3" + (pins DSP4-4 U6-13) + ) + (net "/Seg Logic/SS4_2" + (pins DSP4-6 U6-12) + ) + (net "/Seg Logic/SS4_5" + (pins DSP4-2 U6-11) + ) + (net "/Seg Logic/SS4_1" + (pins DSP4-7 U6-10) + ) + (net "/Seg Logic/SS4_4" + (pins DSP4-3 U6-9) + ) + (net "/Seg Logic/SS4_7" + (pins DSP4-10 U6-7) + ) + (net "/Seg Logic/SS4_6" + (pins DSP4-9 U6-6) + ) + (net "Net-(U6-Pad5)" + (pins U6-5) + ) + (net "Net-(U6-Pad4)" + (pins U6-4) + ) + (net "/Seg Logic/SEGCLK_4" + (pins U2-11 U6-1) + ) + (net "/Seg Logic/SEGCLK_3" + (pins U2-12 U5-1) + ) + (net "Net-(U5-Pad4)" + (pins U5-4) + ) + (net "Net-(U5-Pad5)" + (pins U5-5) + ) + (net "/Seg Logic/SS3_6" + (pins DSP3-9 U5-6) + ) + (net "/Seg Logic/SS3_7" + (pins DSP3-10 U5-7) + ) + (net "/Seg Logic/SS3_4" + (pins DSP3-3 U5-9) + ) + (net "/Seg Logic/SS3_1" + (pins DSP3-7 U5-10) + ) + (net "/Seg Logic/SS3_5" + (pins DSP3-2 U5-11) + ) + (net "/Seg Logic/SS3_2" + (pins DSP3-6 U5-12) + ) + (net "/Seg Logic/SS3_3" + (pins DSP3-4 U5-13) + ) + (net "Net-(U5-Pad14)" + (pins U5-14) + ) + (net "Net-(U4-Pad14)" + (pins U4-14) + ) + (net "/Seg Logic/SS2_3" + (pins DSP2-4 U4-13) + ) + (net "/Seg Logic/SS2_2" + (pins DSP2-6 U4-12) + ) + (net "/Seg Logic/SS2_5" + (pins DSP2-2 U4-11) + ) + (net "/Seg Logic/SS2_1" + (pins DSP2-7 U4-10) + ) + (net "/Seg Logic/SS2_4" + (pins DSP2-3 U4-9) + ) + (net "/Seg Logic/SS2_7" + (pins DSP2-10 U4-7) + ) + (net "/Seg Logic/SS2_6" + (pins DSP2-9 U4-6) + ) + (net "Net-(U4-Pad5)" + (pins U4-5) + ) + (net "Net-(U4-Pad4)" + (pins U4-4) + ) + (net "/Seg Logic/SEGCLK_2" + (pins U2-13 U4-1) + ) + (net "/Seg Logic/SEGCLK_1" + (pins U2-14 U3-1) + ) + (net "Net-(U3-Pad4)" + (pins U3-4) + ) + (net "Net-(U3-Pad5)" + (pins U3-5) + ) + (net "/Seg Logic/SS1_6" + (pins DSP1-9 U3-6) + ) + (net "/Seg Logic/SS1_7" + (pins DSP1-10 U3-7) + ) + (net "/Seg Logic/SS1_4" + (pins DSP1-3 U3-9) + ) + (net "/Seg Logic/SS1_1" + (pins DSP1-7 U3-10) + ) + (net "/Seg Logic/SS1_5" + (pins DSP1-2 U3-11) + ) + (net "/Seg Logic/SS1_2" + (pins DSP1-6 U3-12) + ) + (net "/Seg Logic/SS1_3" + (pins DSP1-4 U3-13) + ) + (net "Net-(U3-Pad14)" + (pins U3-14) + ) + (net 5V_OUT + (pins C3-1 J3-8 J3-7) + ) + (net PWR_BTN + (pins J3-9) + ) + (net SYS_RESET + (pins J3-10) + ) + (net "Net-(J3-Pad15)" + (pins J3-15) + ) + (net "Net-(J3-Pad16)" + (pins J3-16) + ) + (net "Net-(J3-Pad17)" + (pins J3-17) + ) + (net "Net-(J3-Pad18)" + (pins J3-18) + ) + (net "Net-(J3-Pad19)" + (pins J3-19) + ) + (net "Net-(J3-Pad20)" + (pins J3-20) + ) + (net "Net-(J3-Pad21)" + (pins J3-21) + ) + (net "Net-(J3-Pad22)" + (pins J3-22) + ) + (net "Net-(J3-Pad23)" + (pins J3-23) + ) + (net "Net-(J3-Pad24)" + (pins J3-24) + ) + (net "Net-(J3-Pad25)" + (pins J3-25) + ) + (net "Net-(J3-Pad26)" + (pins J3-26) + ) + (net "Net-(J3-Pad27)" + (pins J3-27) + ) + (net "Net-(J3-Pad28)" + (pins J3-28) + ) + (net "Net-(J3-Pad29)" + (pins J3-29) + ) + (net "Net-(J3-Pad30)" + (pins J3-30) + ) + (net "Net-(J3-Pad31)" + (pins J3-31) + ) + (net "Net-(J3-Pad32)" + (pins J3-32) + ) + (net "Net-(J3-Pad33)" + (pins J3-33) + ) + (net "Net-(J3-Pad34)" + (pins J3-34) + ) + (net "Net-(J3-Pad35)" + (pins J3-35) + ) + (net "Net-(J3-Pad36)" + (pins J3-36) + ) + (net "Net-(J3-Pad37)" + (pins J3-37) + ) + (net "Net-(J3-Pad38)" + (pins J3-38) + ) + (net "Net-(J3-Pad39)" + (pins J3-39) + ) + (net "Net-(J3-Pad40)" + (pins J3-40) + ) + (net "Net-(J3-Pad41)" + (pins J3-41) + ) + (net "Net-(J3-Pad42)" + (pins J3-42) + ) + (net "Net-(J1-Pad46)" + (pins J1-46) + ) + (net "Net-(J1-Pad45)" + (pins J1-45) + ) + (net "Net-(J1-Pad44)" + (pins J1-44) + ) + (net "Net-(J1-Pad43)" + (pins J1-43) + ) + (net "Net-(J1-Pad42)" + (pins J1-42) + ) + (net "Net-(J1-Pad41)" + (pins J1-41) + ) + (net "Net-(J1-Pad40)" + (pins J1-40) + ) + (net "Net-(J1-Pad39)" + (pins J1-39) + ) + (net "Net-(J1-Pad38)" + (pins J1-38) + ) + (net "Net-(J1-Pad37)" + (pins J1-37) + ) + (net "Net-(J1-Pad36)" + (pins J1-36) + ) + (net "Net-(J1-Pad35)" + (pins J1-35) + ) + (net "Net-(J1-Pad34)" + (pins J1-34) + ) + (net "Net-(J1-Pad33)" + (pins J1-33) + ) + (net "Net-(J1-Pad32)" + (pins J1-32) + ) + (net "Net-(J1-Pad31)" + (pins J1-31) + ) + (net "Net-(J1-Pad30)" + (pins J1-30) + ) + (net "Net-(J1-Pad29)" + (pins J1-29) + ) + (net "Net-(J1-Pad28)" + (pins J1-28) + ) + (net "Net-(J1-Pad27)" + (pins J1-27) + ) + (net "Net-(J1-Pad26)" + (pins J1-26) + ) + (net "Net-(J1-Pad25)" + (pins J1-25) + ) + (net "Net-(J1-Pad24)" + (pins J1-24) + ) + (net "Net-(J1-Pad23)" + (pins J1-23) + ) + (net "Net-(J1-Pad22)" + (pins J1-22) + ) + (net "Net-(J1-Pad21)" + (pins J1-21) + ) + (net "Net-(J1-Pad20)" + (pins J1-20) + ) + (net "Net-(J1-Pad19)" + (pins J1-19) + ) + (net "Net-(J1-Pad18)" + (pins J1-18) + ) + (net "Net-(J1-Pad17)" + (pins J1-17) + ) + (net "Net-(J1-Pad16)" + (pins J1-16) + ) + (net "Net-(J1-Pad15)" + (pins J1-15) + ) + (net "Net-(J1-Pad14)" + (pins J1-14) + ) + (net "Net-(J1-Pad13)" + (pins J1-13) + ) + (net "Net-(J1-Pad12)" + (pins J1-12) + ) + (net "Net-(J1-Pad11)" + (pins J1-11) + ) + (net "Net-(J1-Pad10)" + (pins J1-10) + ) + (net "Net-(J1-Pad9)" + (pins J1-9) + ) + (net "Net-(J1-Pad8)" + (pins J1-8) + ) + (net "Net-(J1-Pad7)" + (pins J1-7) + ) + (net "Net-(J1-Pad6)" + (pins J1-6) + ) + (net "Net-(J1-Pad5)" + (pins J1-5) + ) + (net "Net-(J1-Pad4)" + (pins J1-4) + ) + (net "Net-(J1-Pad3)" + (pins J1-3) + ) + (class kicad_default "" /SEGSET1_IN_A0 /SEGSET1_IN_A1 /SEGSET1_IN_A2 /SEGSET1_IN_A3 + /SEGSET1_I_0 /SEGSET1_I_1 /SEGSET1_I_2 /SEGSET1_I_3 "/Seg Logic/CD_RST" + "/Seg Logic/SEGCLK_1" "/Seg Logic/SEGCLK_2" "/Seg Logic/SEGCLK_3" "/Seg Logic/SEGCLK_4" + "/Seg Logic/SEGCLK_5" "/Seg Logic/SEGCLK_6" "/Seg Logic/SEGCLK_7" "/Seg Logic/SS1_1" + "/Seg Logic/SS1_2" "/Seg Logic/SS1_3" "/Seg Logic/SS1_4" "/Seg Logic/SS1_5" + "/Seg Logic/SS1_6" "/Seg Logic/SS1_7" "/Seg Logic/SS2_1" "/Seg Logic/SS2_2" + "/Seg Logic/SS2_3" "/Seg Logic/SS2_4" "/Seg Logic/SS2_5" "/Seg Logic/SS2_6" + "/Seg Logic/SS2_7" "/Seg Logic/SS3_1" "/Seg Logic/SS3_2" "/Seg Logic/SS3_3" + "/Seg Logic/SS3_4" "/Seg Logic/SS3_5" "/Seg Logic/SS3_6" "/Seg Logic/SS3_7" + "/Seg Logic/SS4_1" "/Seg Logic/SS4_2" "/Seg Logic/SS4_3" "/Seg Logic/SS4_4" + "/Seg Logic/SS4_5" "/Seg Logic/SS4_6" "/Seg Logic/SS4_7" "/Seg Logic/SS5_1" + "/Seg Logic/SS5_2" "/Seg Logic/SS5_3" "/Seg Logic/SS5_4" "/Seg Logic/SS5_5" + "/Seg Logic/SS5_6" "/Seg Logic/SS5_7" "/Seg Logic/SS6_1" "/Seg Logic/SS6_2" + "/Seg Logic/SS6_3" "/Seg Logic/SS6_4" "/Seg Logic/SS6_5" "/Seg Logic/SS6_6" + "/Seg Logic/SS6_7" "/Seg Logic/SS7_1" "/Seg Logic/SS7_2" "/Seg Logic/SS7_3" + "/Seg Logic/SS7_4" "/Seg Logic/SS7_5" "/Seg Logic/SS7_6" "/Seg Logic/SS7_7" + 3.3_OUT 5V_OUT 5V_SUP GND "Net-(J1-Pad10)" "Net-(J1-Pad11)" "Net-(J1-Pad12)" + "Net-(J1-Pad13)" "Net-(J1-Pad14)" "Net-(J1-Pad15)" "Net-(J1-Pad16)" + "Net-(J1-Pad17)" "Net-(J1-Pad18)" "Net-(J1-Pad19)" "Net-(J1-Pad20)" + "Net-(J1-Pad21)" "Net-(J1-Pad22)" "Net-(J1-Pad23)" "Net-(J1-Pad24)" + "Net-(J1-Pad25)" "Net-(J1-Pad26)" "Net-(J1-Pad27)" "Net-(J1-Pad28)" + "Net-(J1-Pad29)" "Net-(J1-Pad3)" "Net-(J1-Pad30)" "Net-(J1-Pad31)" "Net-(J1-Pad32)" + "Net-(J1-Pad33)" "Net-(J1-Pad34)" "Net-(J1-Pad35)" "Net-(J1-Pad36)" + "Net-(J1-Pad37)" "Net-(J1-Pad38)" "Net-(J1-Pad39)" "Net-(J1-Pad4)" "Net-(J1-Pad40)" + "Net-(J1-Pad41)" "Net-(J1-Pad42)" "Net-(J1-Pad43)" "Net-(J1-Pad44)" + "Net-(J1-Pad45)" "Net-(J1-Pad46)" "Net-(J1-Pad5)" "Net-(J1-Pad6)" "Net-(J1-Pad7)" + "Net-(J1-Pad8)" "Net-(J1-Pad9)" "Net-(J3-Pad15)" "Net-(J3-Pad16)" "Net-(J3-Pad17)" + "Net-(J3-Pad18)" "Net-(J3-Pad19)" "Net-(J3-Pad20)" "Net-(J3-Pad21)" + "Net-(J3-Pad22)" "Net-(J3-Pad23)" "Net-(J3-Pad24)" "Net-(J3-Pad25)" + "Net-(J3-Pad26)" "Net-(J3-Pad27)" "Net-(J3-Pad28)" "Net-(J3-Pad29)" + "Net-(J3-Pad30)" "Net-(J3-Pad31)" "Net-(J3-Pad32)" "Net-(J3-Pad33)" + "Net-(J3-Pad34)" "Net-(J3-Pad35)" "Net-(J3-Pad36)" "Net-(J3-Pad37)" + "Net-(J3-Pad38)" "Net-(J3-Pad39)" "Net-(J3-Pad40)" "Net-(J3-Pad41)" + "Net-(J3-Pad42)" "Net-(U1-Pad11)" "Net-(U1-Pad12)" "Net-(U1-Pad13)" + "Net-(U1-Pad14)" "Net-(U1-Pad16)" "Net-(U1-Pad17)" "Net-(U1-Pad19)" + "Net-(U1-Pad20)" "Net-(U1-Pad22)" "Net-(U1-Pad23)" "Net-(U1-Pad26)" + "Net-(U1-Pad27)" "Net-(U1-Pad29)" "Net-(U1-Pad30)" "Net-(U1-Pad32)" + "Net-(U1-Pad33)" "Net-(U1-Pad35)" "Net-(U1-Pad36)" "Net-(U1-Pad37)" + "Net-(U1-Pad38)" "Net-(U1-Pad40)" "Net-(U1-Pad41)" "Net-(U1-Pad8)" "Net-(U1-Pad9)" + "Net-(U3-Pad14)" "Net-(U3-Pad4)" "Net-(U3-Pad5)" "Net-(U4-Pad14)" "Net-(U4-Pad4)" + "Net-(U4-Pad5)" "Net-(U5-Pad14)" "Net-(U5-Pad4)" "Net-(U5-Pad5)" "Net-(U6-Pad14)" + "Net-(U6-Pad4)" "Net-(U6-Pad5)" "Net-(U7-Pad14)" "Net-(U7-Pad4)" "Net-(U7-Pad5)" + "Net-(U8-Pad14)" "Net-(U8-Pad4)" "Net-(U8-Pad5)" "Net-(U9-Pad14)" "Net-(U9-Pad4)" + "Net-(U9-Pad5)" PWR_BTN SYS_RESET + (circuit + (use_via Via[0-1]_800:400_um) + ) + (rule + (width 250) + (clearance 200.1) + ) + ) + ) + (wiring + ) +) diff --git a/bort-segs.pro b/bort-segs.pro index 152769c..62d2759 100644 --- a/bort-segs.pro +++ b/bort-segs.pro @@ -1,33 +1,43 @@ -update=22/05/2015 07:44:53 -version=1 -last_client=kicad -[general] -version=1 -RootSch= -BoardNm= -[pcbnew] -version=1 -LastNetListRead= -UseCmpFile=1 -PadDrill=0.600000000000 -PadDrillOvalY=0.600000000000 -PadSizeH=1.500000000000 -PadSizeV=1.500000000000 -PcbTextSizeV=1.500000000000 -PcbTextSizeH=1.500000000000 -PcbTextThickness=0.300000000000 -ModuleTextSizeV=1.000000000000 -ModuleTextSizeH=1.000000000000 -ModuleTextSizeThickness=0.150000000000 -SolderMaskClearance=0.000000000000 -SolderMaskMinWidth=0.000000000000 -DrawSegmentWidth=0.200000000000 -BoardOutlineThickness=0.100000000000 -ModuleOutlineThickness=0.150000000000 -[cvpcb] -version=1 -NetIExt=net -[eeschema] -version=1 -LibDir= -[eeschema/libraries] +update=1/11/2019 7:41:40 AM +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName=Pcbnew +SpiceAjustPassiveValues=0 +LabSize=50 +ERC_TestSimilarLabels=1 diff --git a/printme/hat.pdf b/printme/hat.pdf new file mode 100644 index 0000000..80e673b Binary files /dev/null and b/printme/hat.pdf differ diff --git a/printme/hat2.pdf b/printme/hat2.pdf new file mode 100644 index 0000000..9329cae Binary files /dev/null and b/printme/hat2.pdf differ diff --git a/printme/hat3.pdf b/printme/hat3.pdf new file mode 100644 index 0000000..930c226 Binary files /dev/null and b/printme/hat3.pdf differ