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629d050f IS |
1 | #----------------------------------------------------------- |
2 | # Vivado v2019.1 (64-bit) | |
3 | # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 | |
4 | # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 | |
5 | # Start of session at: Tue Aug 13 10:39:28 2019 | |
6 | # Process ID: 13936 | |
7 | # Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1 | |
8 | # Command line: vivado.exe -log esdi_ctl_phy.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace | |
9 | # Log file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy.vdi | |
10 | # Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1\vivado.jou | |
11 | #----------------------------------------------------------- | |
12 | source esdi_ctl_phy.tcl -notrace | |
13 | Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1 | |
14 | Design is defaulting to srcset: sources_1 | |
15 | Design is defaulting to constrset: constrs_1 | |
16 | INFO: [Device 21-403] Loading part xc7z007sclg225-1 | |
17 | INFO: [Project 1-479] Netlist was created with Vivado 2019.1 | |
18 | INFO: [Project 1-570] Preparing netlist for logic optimization | |
19 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000 | |
20 | INFO: [Project 1-111] Unisim Transformation Summary: | |
21 | No Unisim elements were transformed. | |
22 | ||
23 | 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
24 | link_design completed successfully | |
25 | link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582 | |
26 | Command: opt_design | |
27 | Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' | |
28 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' | |
29 | Running DRC as a precondition to command opt_design | |
30 | ||
31 | Starting DRC Task | |
32 | INFO: [DRC 23-27] Running DRC with 2 threads | |
33 | INFO: [Project 1-461] DRC finished with 0 Errors | |
34 | INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. | |
35 | ||
36 | Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824 | |
37 | ||
38 | Starting Cache Timing Information Task | |
39 | INFO: [Timing 38-35] Done setting XDC timing constraints. | |
40 | Ending Cache Timing Information Task | Checksum: 686e1c75 | |
41 | ||
42 | Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363 | |
43 | ||
44 | Starting Logic Optimization Task | |
45 | ||
46 | Phase 1 Retarget | |
47 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
48 | INFO: [Opt 31-49] Retargeted 0 cell(s). | |
49 | Phase 1 Retarget | Checksum: 686e1c75 | |
50 | ||
51 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
52 | INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells | |
53 | ||
54 | Phase 2 Constant propagation | |
55 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). | |
56 | Phase 2 Constant propagation | Checksum: 686e1c75 | |
57 | ||
58 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
59 | INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells | |
60 | ||
61 | Phase 3 Sweep | |
62 | Phase 3 Sweep | Checksum: 686e1c75 | |
63 | ||
64 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
65 | INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells | |
66 | ||
67 | Phase 4 BUFG optimization | |
68 | Phase 4 BUFG optimization | Checksum: 686e1c75 | |
69 | ||
70 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
71 | INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. | |
72 | ||
73 | Phase 5 Shift Register Optimization | |
74 | INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs | |
75 | Phase 5 Shift Register Optimization | Checksum: 686e1c75 | |
76 | ||
77 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
78 | INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells | |
79 | ||
80 | Phase 6 Post Processing Netlist | |
81 | Phase 6 Post Processing Netlist | Checksum: 686e1c75 | |
82 | ||
83 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
84 | INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells | |
85 | Opt_design Change Summary | |
86 | ========================= | |
87 | ||
88 | ||
89 | ------------------------------------------------------------------------------------------------------------------------- | |
90 | | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | | |
91 | ------------------------------------------------------------------------------------------------------------------------- | |
92 | | Retarget | 0 | 0 | 0 | | |
93 | | Constant propagation | 0 | 0 | 0 | | |
94 | | Sweep | 0 | 0 | 0 | | |
95 | | BUFG optimization | 0 | 0 | 0 | | |
96 | | Shift Register Optimization | 0 | 0 | 0 | | |
97 | | Post Processing Netlist | 0 | 0 | 0 | | |
98 | ------------------------------------------------------------------------------------------------------------------------- | |
99 | ||
100 | ||
101 | ||
102 | Starting Connectivity Check Task | |
103 | ||
104 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
105 | Ending Logic Optimization Task | Checksum: 686e1c75 | |
106 | ||
107 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781 | |
108 | ||
109 | Starting Power Optimization Task | |
110 | INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. | |
111 | Ending Power Optimization Task | Checksum: 686e1c75 | |
112 | ||
113 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
114 | ||
115 | Starting Final Cleanup Task | |
116 | Ending Final Cleanup Task | Checksum: 686e1c75 | |
117 | ||
118 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
119 | ||
120 | Starting Netlist Obfuscation Task | |
121 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
122 | Ending Netlist Obfuscation Task | Checksum: 686e1c75 | |
123 | ||
124 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
125 | INFO: [Common 17-83] Releasing license: Implementation | |
126 | 21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. | |
127 | opt_design completed successfully | |
128 | opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559 | |
129 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 | |
130 | WARNING: [Constraints 18-5210] No constraints selected for write. | |
131 | Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. | |
132 | INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated. | |
133 | INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx | |
134 | Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx | |
135 | INFO: [IP_Flow 19-234] Refreshing IP repositories | |
136 | INFO: [IP_Flow 19-1704] No user IP repositories specified | |
137 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'. | |
138 | INFO: [DRC 23-27] Running DRC with 2 threads | |
139 | INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt. | |
140 | report_drc completed successfully | |
141 | Command: place_design | |
142 | Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' | |
143 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' | |
144 | INFO: [DRC 23-27] Running DRC with 2 threads | |
145 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
146 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
147 | Running DRC as a precondition to command place_design | |
148 | INFO: [DRC 23-27] Running DRC with 2 threads | |
149 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors | |
150 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. | |
151 | ||
152 | Starting Placer Task | |
153 | INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs | |
154 | ||
155 | Phase 1 Placer Initialization | |
156 | ||
157 | Phase 1.1 Placer Initialization Netlist Sorting | |
158 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000 | |
159 | Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 | |
160 | ||
161 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000 | |
162 | Phase 1 Placer Initialization | Checksum: 00000000 | |
163 | ||
164 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000 | |
165 | ERROR: [Place 30-494] The design is empty | |
166 | Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. | |
167 | Ending Placer Task | Checksum: 00000000 | |
168 | ||
169 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000 | |
170 | INFO: [Common 17-83] Releasing license: Implementation | |
171 | 37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. | |
172 | place_design failed | |
173 | ERROR: [Common 17-69] Command failed: Placer could not place all instances | |
174 | INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019... |