projects / esdi.git / blame
| Commit | Line | Data |
|---|---|---|
| 629d050f IS |
1 | Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. |
| 2 | --------------------------------------------------------------------------------------------------------------------------- | |
| 3 | | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 | |
| 4 | | Date : Tue Aug 13 10:39:56 2019 | |
| 5 | | Host : KREMLINMACHINE running 64-bit major release (build 9200) | |
| 6 | | Command : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx | |
| 7 | | Design : esdi_ctl_phy | |
| 8 | | Device : xc7z007sclg225-1 | |
| 9 | | Speed File : -1 | |
| 10 | | Design State : Fully Routed | |
| 11 | --------------------------------------------------------------------------------------------------------------------------- | |
| 12 | ||
| 13 | Report DRC | |
| 14 | ||
| 15 | Table of Contents | |
| 16 | ----------------- | |
| 17 | 1. REPORT SUMMARY | |
| 18 | 2. REPORT DETAILS | |
| 19 | ||
| 20 | 1. REPORT SUMMARY | |
| 21 | ----------------- | |
| 22 | Netlist: netlist | |
| 23 | Floorplan: design_1 | |
| 24 | Design limits: <entire design considered> | |
| 25 | Ruledeck: default | |
| 26 | Max violations: <unlimited> | |
| 27 | Violations found: 1 | |
| 28 | +--------+----------+--------------------+------------+ | |
| 29 | | Rule | Severity | Description | Violations | | |
| 30 | +--------+----------+--------------------+------------+ | |
| 31 | | ZPS7-1 | Warning | PS7 block required | 1 | | |
| 32 | +--------+----------+--------------------+------------+ | |
| 33 | ||
| 34 | 2. REPORT DETAILS | |
| 35 | ----------------- | |
| 36 | ZPS7-1#1 Warning | |
| 37 | PS7 block required | |
| 38 | The PS7 cell must be used in this Zynq design in order to enable correct default configuration. | |
| 39 | Related violations: <none> | |
| 40 | ||
| 41 |