projects / esdi.git / blame
| Commit | Line | Data |
|---|---|---|
| 629d050f IS |
1 | # \r |
| 2 | # Synthesis run script generated by Vivado\r | |
| 3 | # \r | |
| 4 | \r | |
| 5 | set TIME_start [clock seconds] \r | |
| 6 | proc create_report { reportName command } {\r | |
| 7 | set status "."\r | |
| 8 | append status $reportName ".fail"\r | |
| 9 | if { [file exists $status] } {\r | |
| 10 | eval file delete [glob $status]\r | |
| 11 | }\r | |
| 12 | send_msg_id runtcl-4 info "Executing : $command"\r | |
| 13 | set retval [eval catch { $command } msg]\r | |
| 14 | if { $retval != 0 } {\r | |
| 15 | set fp [open $status w]\r | |
| 16 | close $fp\r | |
| 17 | send_msg_id runtcl-5 warning "$msg"\r | |
| 18 | }\r | |
| 19 | }\r | |
| 20 | create_project -in_memory -part xc7z007sclg225-1\r | |
| 21 | \r | |
| 22 | set_param project.singleFileAddWarning.threshold 0\r | |
| 23 | set_param project.compositeFile.enableAutoGeneration 0\r | |
| 24 | set_param synth.vivado.isSynthRun true\r | |
| 25 | set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project]\r | |
| 26 | set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project]\r | |
| 27 | set_property default_lib xil_defaultlib [current_project]\r | |
| 28 | set_property target_language Verilog [current_project]\r | |
| 29 | set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project]\r | |
| 30 | set_property board_part em.avnet.com:minized:part0:1.2 [current_project]\r | |
| 31 | set_property ip_output_repo s:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project]\r | |
| 32 | set_property ip_cache_permissions {read write} [current_project]\r | |
| 33 | read_verilog -library xil_defaultlib S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v\r | |
| 34 | # Mark all dcp files as not used in implementation to prevent them from being\r | |
| 35 | # stitched into the results of this synthesis run. Any black boxes in the\r | |
| 36 | # design are intentionally left as such for best results. Dcp files will be\r | |
| 37 | # stitched into the design at a later time, either when this synthesis run is\r | |
| 38 | # opened, or when it is stitched into a dependent implementation run.\r | |
| 39 | foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {\r | |
| 40 | set_property used_in_implementation false $dcp\r | |
| 41 | }\r | |
| 42 | set_param ips.enableIPCacheLiteLoad 1\r | |
| 43 | close [open __synthesis_is_running__ w]\r | |
| 44 | \r | |
| 45 | synth_design -top esdi_ctl_phy -part xc7z007sclg225-1\r | |
| 46 | \r | |
| 47 | \r | |
| 48 | # disable binary constraint mode for synth run checkpoints\r | |
| 49 | set_param constraints.enableBinaryConstraints false\r | |
| 50 | write_checkpoint -force -noxdef esdi_ctl_phy.dcp\r | |
| 51 | create_report "synth_1_synth_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb"\r | |
| 52 | file delete __synthesis_is_running__\r | |
| 53 | close [open __synthesis_is_complete__ w]\r |