initial
[esdi.git] / esdi.runs / synth_1 / runme.log
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1\r
2*** Running vivado\r
3 with args -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl\r
4\r
5\r
6****** Vivado v2019.1 (64-bit)\r
7 **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019\r
8 **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019\r
9 ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
10\r
11source esdi_ctl_phy.tcl -notrace\r
12Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
13Starting synth_design\r
14Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s'\r
15INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s'\r
16INFO: Launching helper process for spawning children vivado processes\r
17INFO: Helper process launched with PID 18332 \r
18---------------------------------------------------------------------------------\r
19Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551\r
20---------------------------------------------------------------------------------\r
21INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]\r
22INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]\r
23WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module\r
24---------------------------------------------------------------------------------\r
25Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
26---------------------------------------------------------------------------------\r
27---------------------------------------------------------------------------------\r
28Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
29---------------------------------------------------------------------------------\r
30---------------------------------------------------------------------------------\r
31Start Loading Part and Timing Information\r
32---------------------------------------------------------------------------------\r
33Loading part: xc7z007sclg225-1\r
34---------------------------------------------------------------------------------\r
35Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
36---------------------------------------------------------------------------------\r
37INFO: [Device 21-403] Loading part xc7z007sclg225-1\r
38---------------------------------------------------------------------------------\r
39Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852\r
40---------------------------------------------------------------------------------\r
41\r
42Report RTL Partitions: \r
43+-+--------------+------------+----------+\r
44| |RTL Partition |Replication |Instances |\r
45+-+--------------+------------+----------+\r
46+-+--------------+------------+----------+\r
47No constraint files found.\r
48---------------------------------------------------------------------------------\r
49Start RTL Component Statistics \r
50---------------------------------------------------------------------------------\r
51Detailed RTL Component Info : \r
52---------------------------------------------------------------------------------\r
53Finished RTL Component Statistics \r
54---------------------------------------------------------------------------------\r
55---------------------------------------------------------------------------------\r
56Start RTL Hierarchical Component Statistics \r
57---------------------------------------------------------------------------------\r
58Hierarchical RTL Component report \r
59---------------------------------------------------------------------------------\r
60Finished RTL Hierarchical Component Statistics\r
61---------------------------------------------------------------------------------\r
62---------------------------------------------------------------------------------\r
63Start Part Resource Summary\r
64---------------------------------------------------------------------------------\r
65Part Resources:\r
66DSPs: 66 (col length:40)\r
67BRAMs: 100 (col length: RAMB18 40 RAMB36 20)\r
68---------------------------------------------------------------------------------\r
69Finished Part Resource Summary\r
70---------------------------------------------------------------------------------\r
71No constraint files found.\r
72---------------------------------------------------------------------------------\r
73Start Cross Boundary and Area Optimization\r
74---------------------------------------------------------------------------------\r
75Warning: Parallel synthesis criteria is not met \r
76WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module\r
77---------------------------------------------------------------------------------\r
78Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
79---------------------------------------------------------------------------------\r
80\r
81Report RTL Partitions: \r
82+-+--------------+------------+----------+\r
83| |RTL Partition |Replication |Instances |\r
84+-+--------------+------------+----------+\r
85+-+--------------+------------+----------+\r
86No constraint files found.\r
87---------------------------------------------------------------------------------\r
88Start Timing Optimization\r
89---------------------------------------------------------------------------------\r
90---------------------------------------------------------------------------------\r
91Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
92---------------------------------------------------------------------------------\r
93\r
94Report RTL Partitions: \r
95+-+--------------+------------+----------+\r
96| |RTL Partition |Replication |Instances |\r
97+-+--------------+------------+----------+\r
98+-+--------------+------------+----------+\r
99---------------------------------------------------------------------------------\r
100Start Technology Mapping\r
101---------------------------------------------------------------------------------\r
102---------------------------------------------------------------------------------\r
103Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
104---------------------------------------------------------------------------------\r
105\r
106Report RTL Partitions: \r
107+-+--------------+------------+----------+\r
108| |RTL Partition |Replication |Instances |\r
109+-+--------------+------------+----------+\r
110+-+--------------+------------+----------+\r
111---------------------------------------------------------------------------------\r
112Start IO Insertion\r
113---------------------------------------------------------------------------------\r
114---------------------------------------------------------------------------------\r
115Start Flattening Before IO Insertion\r
116---------------------------------------------------------------------------------\r
117---------------------------------------------------------------------------------\r
118Finished Flattening Before IO Insertion\r
119---------------------------------------------------------------------------------\r
120---------------------------------------------------------------------------------\r
121Start Final Netlist Cleanup\r
122---------------------------------------------------------------------------------\r
123---------------------------------------------------------------------------------\r
124Finished Final Netlist Cleanup\r
125---------------------------------------------------------------------------------\r
126---------------------------------------------------------------------------------\r
127Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
128---------------------------------------------------------------------------------\r
129\r
130Report Check Netlist: \r
131+------+------------------+-------+---------+-------+------------------+\r
132| |Item |Errors |Warnings |Status |Description |\r
133+------+------------------+-------+---------+-------+------------------+\r
134|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets |\r
135+------+------------------+-------+---------+-------+------------------+\r
136---------------------------------------------------------------------------------\r
137Start Renaming Generated Instances\r
138---------------------------------------------------------------------------------\r
139---------------------------------------------------------------------------------\r
140Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
141---------------------------------------------------------------------------------\r
142\r
143Report RTL Partitions: \r
144+-+--------------+------------+----------+\r
145| |RTL Partition |Replication |Instances |\r
146+-+--------------+------------+----------+\r
147+-+--------------+------------+----------+\r
148---------------------------------------------------------------------------------\r
149Start Rebuilding User Hierarchy\r
150---------------------------------------------------------------------------------\r
151---------------------------------------------------------------------------------\r
152Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
153---------------------------------------------------------------------------------\r
154---------------------------------------------------------------------------------\r
155Start Renaming Generated Ports\r
156---------------------------------------------------------------------------------\r
157---------------------------------------------------------------------------------\r
158Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
159---------------------------------------------------------------------------------\r
160---------------------------------------------------------------------------------\r
161Start Handling Custom Attributes\r
162---------------------------------------------------------------------------------\r
163---------------------------------------------------------------------------------\r
164Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
165---------------------------------------------------------------------------------\r
166---------------------------------------------------------------------------------\r
167Start Renaming Generated Nets\r
168---------------------------------------------------------------------------------\r
169---------------------------------------------------------------------------------\r
170Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
171---------------------------------------------------------------------------------\r
172---------------------------------------------------------------------------------\r
173Start Writing Synthesis Report\r
174---------------------------------------------------------------------------------\r
175\r
176Report BlackBoxes: \r
177+-+--------------+----------+\r
178| |BlackBox name |Instances |\r
179+-+--------------+----------+\r
180+-+--------------+----------+\r
181\r
182Report Cell Usage: \r
183+------+-------------+------+\r
184| |Cell |Count |\r
185+------+-------------+------+\r
186|1 |esdi_ctl_phy | 1|\r
187+------+-------------+------+\r
188\r
189Report Instance Areas: \r
190+------+---------+-------+------+\r
191| |Instance |Module |Cells |\r
192+------+---------+-------+------+\r
193|1 |top | | 0|\r
194+------+---------+-------+------+\r
195---------------------------------------------------------------------------------\r
196Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
197---------------------------------------------------------------------------------\r
198Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.\r
199Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
200Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
201INFO: [Project 1-571] Translating synthesized netlist\r
202INFO: [Project 1-570] Preparing netlist for logic optimization\r
203INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
204Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000\r
205INFO: [Project 1-111] Unisim Transformation Summary:\r
206No Unisim elements were transformed.\r
207\r
208INFO: [Common 17-83] Releasing license: Synthesis\r
2099 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
210synth_design completed successfully\r
211synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191\r
212Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000\r
213WARNING: [Constraints 18-5210] No constraints selected for write.\r
214Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.\r
215INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated.\r
216INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb\r
217INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019...\r