initial

[esdi.git] / esdi.srcs / sources_1 / new / esdi_phy_ctl.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 08/06/2019 10:50:49 PM
// Design Name: 
// Module Name: esdi_phy
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module esdi_ctl_phy (
    output head_sel_2p3,
    output head_sel_2p2,
    output write_gate,
    input cfg_stat,
    input xfer_ack,
    input attn,
    output head_sel_2p0,
    input sector_found,
    output head_sel_2p1,
    input index,
    input rdy,
    output xfer_req,
    output drive_sel_2p0,
    output drive_sel_2p1,
    output drive_sel_2p2,
    output read_gate,
    output cmd_data
    );
endmodule