| 1 | `timescale 1ns / 1ps |
| 2 | ////////////////////////////////////////////////////////////////////////////////// |
| 3 | // Company: |
| 4 | // Engineer: |
| 5 | // |
| 6 | // Create Date: 08/06/2019 10:50:49 PM |
| 7 | // Design Name: |
| 8 | // Module Name: esdi_phy |
| 9 | // Project Name: |
| 10 | // Target Devices: |
| 11 | // Tool Versions: |
| 12 | // Description: |
| 13 | // |
| 14 | // Dependencies: |
| 15 | // |
| 16 | // Revision: |
| 17 | // Revision 0.01 - File Created |
| 18 | // Additional Comments: |
| 19 | // |
| 20 | ////////////////////////////////////////////////////////////////////////////////// |
| 21 | |
| 22 | |
| 23 | module esdi_ctl_phy ( |
| 24 | output head_sel_2p3, |
| 25 | output head_sel_2p2, |
| 26 | output write_gate, |
| 27 | input cfg_stat, |
| 28 | input xfer_ack, |
| 29 | input attn, |
| 30 | output head_sel_2p0, |
| 31 | input sector_found, |
| 32 | output head_sel_2p1, |
| 33 | input index, |
| 34 | input rdy, |
| 35 | output xfer_req, |
| 36 | output drive_sel_2p0, |
| 37 | output drive_sel_2p1, |
| 38 | output drive_sel_2p2, |
| 39 | output read_gate, |
| 40 | output cmd_data |
| 41 | ); |
| 42 | endmodule |