esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt

   1 Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
   2 -------------------------------------------------------------------------------------------------------------------
   3 | Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
   4 | Date         : Tue Aug 13 10:39:11 2019
   5 | Host         : KREMLINMACHINE running 64-bit major release  (build 9200)
   6 | Command      : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb
   7 | Design       : esdi_ctl_phy
   8 | Device       : 7z007sclg225-1
   9 | Design State : Fully Placed
  10 -------------------------------------------------------------------------------------------------------------------
  11
  12 Utilization Design Information
  13
  14 Table of Contents
  15 -----------------
  16 1. Slice Logic
  17 1.1 Summary of Registers by Type
  18 2. Slice Logic Distribution
  19 3. Memory
  20 4. DSP
  21 5. IO and GT Specific
  22 6. Clocking
  23 7. Specific Feature
  24 8. Primitives
  25 9. Black Boxes
  26 10. Instantiated Netlists
  27
  28 1. Slice Logic
  29 --------------
  30
  31 +-------------------------+------+-------+-----------+-------+
  32 |        Site Type        | Used | Fixed | Available | Util% |
  33 +-------------------------+------+-------+-----------+-------+
  34 | Slice LUTs              |    0 |     0 |     14400 |  0.00 |
  35 |   LUT as Logic          |    0 |     0 |     14400 |  0.00 |
  36 |   LUT as Memory         |    0 |     0 |      6000 |  0.00 |
  37 | Slice Registers         |    0 |     0 |     28800 |  0.00 |
  38 |   Register as Flip Flop |    0 |     0 |     28800 |  0.00 |
  39 |   Register as Latch     |    0 |     0 |     28800 |  0.00 |
  40 | F7 Muxes                |    0 |     0 |      8800 |  0.00 |
  41 | F8 Muxes                |    0 |     0 |      4400 |  0.00 |
  42 +-------------------------+------+-------+-----------+-------+
  43
  44
  45 1.1 Summary of Registers by Type
  46 --------------------------------
  47
  48 +-------+--------------+-------------+--------------+
  49 | Total | Clock Enable | Synchronous | Asynchronous |
  50 +-------+--------------+-------------+--------------+
  51 | 0     |            _ |           - |            - |
  52 | 0     |            _ |           - |          Set |
  53 | 0     |            _ |           - |        Reset |
  54 | 0     |            _ |         Set |            - |
  55 | 0     |            _ |       Reset |            - |
  56 | 0     |          Yes |           - |            - |
  57 | 0     |          Yes |           - |          Set |
  58 | 0     |          Yes |           - |        Reset |
  59 | 0     |          Yes |         Set |            - |
  60 | 0     |          Yes |       Reset |            - |
  61 +-------+--------------+-------------+--------------+
  62
  63
  64 2. Slice Logic Distribution
  65 ---------------------------
  66
  67 +------------------------------------------+------+-------+-----------+-------+
  68 |                 Site Type                | Used | Fixed | Available | Util% |
  69 +------------------------------------------+------+-------+-----------+-------+
  70 | Slice                                    |    0 |     0 |      4400 |  0.00 |
  71 |   SLICEL                                 |    0 |     0 |           |       |
  72 |   SLICEM                                 |    0 |     0 |           |       |
  73 | LUT as Logic                             |    0 |     0 |     14400 |  0.00 |
  74 | LUT as Memory                            |    0 |     0 |      6000 |  0.00 |
  75 |   LUT as Distributed RAM                 |    0 |     0 |           |       |
  76 |   LUT as Shift Register                  |    0 |     0 |           |       |
  77 | Slice Registers                          |    0 |     0 |     28800 |  0.00 |
  78 |   Register driven from within the Slice  |    0 |       |           |       |
  79 |   Register driven from outside the Slice |    0 |       |           |       |
  80 | Unique Control Sets                      |    0 |       |      4400 |  0.00 |
  81 +------------------------------------------+------+-------+-----------+-------+
  82 * Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
  83
  84
  85 3. Memory
  86 ---------
  87
  88 +----------------+------+-------+-----------+-------+
  89 |    Site Type   | Used | Fixed | Available | Util% |
  90 +----------------+------+-------+-----------+-------+
  91 | Block RAM Tile |    0 |     0 |        50 |  0.00 |
  92 |   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
  93 |   RAMB18       |    0 |     0 |       100 |  0.00 |
  94 +----------------+------+-------+-----------+-------+
  95 * Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
  96
  97
  98 4. DSP
  99 ------
 100
 101 +-----------+------+-------+-----------+-------+
 102 | Site Type | Used | Fixed | Available | Util% |
 103 +-----------+------+-------+-----------+-------+
 104 | DSPs      |    0 |     0 |        66 |  0.00 |
 105 +-----------+------+-------+-----------+-------+
 106
 107
 108 5. IO and GT Specific
 109 ---------------------
 110
 111 +-----------------------------+------+-------+-----------+-------+
 112 |          Site Type          | Used | Fixed | Available | Util% |
 113 +-----------------------------+------+-------+-----------+-------+
 114 | Bonded IOB                  |    0 |     0 |        54 |  0.00 |
 115 | Bonded IPADs                |    0 |     0 |         2 |  0.00 |
 116 | Bonded IOPADs               |    0 |     0 |       130 |  0.00 |
 117 | PHY_CONTROL                 |    0 |     0 |         2 |  0.00 |
 118 | PHASER_REF                  |    0 |     0 |         2 |  0.00 |
 119 | OUT_FIFO                    |    0 |     0 |         8 |  0.00 |
 120 | IN_FIFO                     |    0 |     0 |         8 |  0.00 |
 121 | IDELAYCTRL                  |    0 |     0 |         2 |  0.00 |
 122 | IBUFDS                      |    0 |     0 |        54 |  0.00 |
 123 | PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |         8 |  0.00 |
 124 | PHASER_IN/PHASER_IN_PHY     |    0 |     0 |         8 |  0.00 |
 125 | IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       100 |  0.00 |
 126 | ILOGIC                      |    0 |     0 |        54 |  0.00 |
 127 | OLOGIC                      |    0 |     0 |        54 |  0.00 |
 128 +-----------------------------+------+-------+-----------+-------+
 129
 130
 131 6. Clocking
 132 -----------
 133
 134 +------------+------+-------+-----------+-------+
 135 |  Site Type | Used | Fixed | Available | Util% |
 136 +------------+------+-------+-----------+-------+
 137 | BUFGCTRL   |    0 |     0 |        32 |  0.00 |
 138 | BUFIO      |    0 |     0 |         8 |  0.00 |
 139 | MMCME2_ADV |    0 |     0 |         2 |  0.00 |
 140 | PLLE2_ADV  |    0 |     0 |         2 |  0.00 |
 141 | BUFMRCE    |    0 |     0 |         4 |  0.00 |
 142 | BUFHCE     |    0 |     0 |        48 |  0.00 |
 143 | BUFR       |    0 |     0 |         8 |  0.00 |
 144 +------------+------+-------+-----------+-------+
 145
 146
 147 7. Specific Feature
 148 -------------------
 149
 150 +-------------+------+-------+-----------+-------+
 151 |  Site Type  | Used | Fixed | Available | Util% |
 152 +-------------+------+-------+-----------+-------+
 153 | BSCANE2     |    0 |     0 |         4 |  0.00 |
 154 | CAPTUREE2   |    0 |     0 |         1 |  0.00 |
 155 | DNA_PORT    |    0 |     0 |         1 |  0.00 |
 156 | EFUSE_USR   |    0 |     0 |         1 |  0.00 |
 157 | FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
 158 | ICAPE2      |    0 |     0 |         2 |  0.00 |
 159 | STARTUPE2   |    0 |     0 |         1 |  0.00 |
 160 | XADC        |    0 |     0 |         1 |  0.00 |
 161 +-------------+------+-------+-----------+-------+
 162
 163
 164 8. Primitives
 165 -------------
 166
 167 +----------+------+---------------------+
 168 | Ref Name | Used | Functional Category |
 169 +----------+------+---------------------+
 170
 171
 172 9. Black Boxes
 173 --------------
 174
 175 +----------+------+
 176 | Ref Name | Used |
 177 +----------+------+
 178
 179
 180 10. Instantiated Netlists
 181 -------------------------
 182
 183 +----------+------+
 184 | Ref Name | Used |
 185 +----------+------+
 186
 187