esdi.runs/synth_1/runme.log

   1
   2 *** Running vivado
   3     with args -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl
   4
   5
   6 ****** Vivado v2019.1 (64-bit)
   7   **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
   8   **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
   9     ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  10
  11 source esdi_ctl_phy.tcl -notrace
  12 Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1
  13 Starting synth_design
  14 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s'
  15 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s'
  16 INFO: Launching helper process for spawning children vivado processes
  17 INFO: Helper process launched with PID 18332
  18 ---------------------------------------------------------------------------------
  19 Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551
  20 ---------------------------------------------------------------------------------
  21 INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
  22 INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
  23 WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
  24 ---------------------------------------------------------------------------------
  25 Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  26 ---------------------------------------------------------------------------------
  27 ---------------------------------------------------------------------------------
  28 Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  29 ---------------------------------------------------------------------------------
  30 ---------------------------------------------------------------------------------
  31 Start Loading Part and Timing Information
  32 ---------------------------------------------------------------------------------
  33 Loading part: xc7z007sclg225-1
  34 ---------------------------------------------------------------------------------
  35 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  36 ---------------------------------------------------------------------------------
  37 INFO: [Device 21-403] Loading part xc7z007sclg225-1
  38 ---------------------------------------------------------------------------------
  39 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852
  40 ---------------------------------------------------------------------------------
  41
  42 Report RTL Partitions:
  43 +-+--------------+------------+----------+
  44 | |RTL Partition |Replication |Instances |
  45 +-+--------------+------------+----------+
  46 +-+--------------+------------+----------+
  47 No constraint files found.
  48 ---------------------------------------------------------------------------------
  49 Start RTL Component Statistics
  50 ---------------------------------------------------------------------------------
  51 Detailed RTL Component Info :
  52 ---------------------------------------------------------------------------------
  53 Finished RTL Component Statistics
  54 ---------------------------------------------------------------------------------
  55 ---------------------------------------------------------------------------------
  56 Start RTL Hierarchical Component Statistics
  57 ---------------------------------------------------------------------------------
  58 Hierarchical RTL Component report
  59 ---------------------------------------------------------------------------------
  60 Finished RTL Hierarchical Component Statistics
  61 ---------------------------------------------------------------------------------
  62 ---------------------------------------------------------------------------------
  63 Start Part Resource Summary
  64 ---------------------------------------------------------------------------------
  65 Part Resources:
  66 DSPs: 66 (col length:40)
  67 BRAMs: 100 (col length: RAMB18 40 RAMB36 20)
  68 ---------------------------------------------------------------------------------
  69 Finished Part Resource Summary
  70 ---------------------------------------------------------------------------------
  71 No constraint files found.
  72 ---------------------------------------------------------------------------------
  73 Start Cross Boundary and Area Optimization
  74 ---------------------------------------------------------------------------------
  75 Warning: Parallel synthesis criteria is not met
  76 WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
  77 ---------------------------------------------------------------------------------
  78 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
  79 ---------------------------------------------------------------------------------
  80
  81 Report RTL Partitions:
  82 +-+--------------+------------+----------+
  83 | |RTL Partition |Replication |Instances |
  84 +-+--------------+------------+----------+
  85 +-+--------------+------------+----------+
  86 No constraint files found.
  87 ---------------------------------------------------------------------------------
  88 Start Timing Optimization
  89 ---------------------------------------------------------------------------------
  90 ---------------------------------------------------------------------------------
  91 Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
  92 ---------------------------------------------------------------------------------
  93
  94 Report RTL Partitions:
  95 +-+--------------+------------+----------+
  96 | |RTL Partition |Replication |Instances |
  97 +-+--------------+------------+----------+
  98 +-+--------------+------------+----------+
  99 ---------------------------------------------------------------------------------
 100 Start Technology Mapping
 101 ---------------------------------------------------------------------------------
 102 ---------------------------------------------------------------------------------
 103 Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
 104 ---------------------------------------------------------------------------------
 105
 106 Report RTL Partitions:
 107 +-+--------------+------------+----------+
 108 | |RTL Partition |Replication |Instances |
 109 +-+--------------+------------+----------+
 110 +-+--------------+------------+----------+
 111 ---------------------------------------------------------------------------------
 112 Start IO Insertion
 113 ---------------------------------------------------------------------------------
 114 ---------------------------------------------------------------------------------
 115 Start Flattening Before IO Insertion
 116 ---------------------------------------------------------------------------------
 117 ---------------------------------------------------------------------------------
 118 Finished Flattening Before IO Insertion
 119 ---------------------------------------------------------------------------------
 120 ---------------------------------------------------------------------------------
 121 Start Final Netlist Cleanup
 122 ---------------------------------------------------------------------------------
 123 ---------------------------------------------------------------------------------
 124 Finished Final Netlist Cleanup
 125 ---------------------------------------------------------------------------------
 126 ---------------------------------------------------------------------------------
 127 Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 128 ---------------------------------------------------------------------------------
 129
 130 Report Check Netlist:
 131 +------+------------------+-------+---------+-------+------------------+
 132 |      |Item              |Errors |Warnings |Status |Description       |
 133 +------+------------------+-------+---------+-------+------------------+
 134 |1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
 135 +------+------------------+-------+---------+-------+------------------+
 136 ---------------------------------------------------------------------------------
 137 Start Renaming Generated Instances
 138 ---------------------------------------------------------------------------------
 139 ---------------------------------------------------------------------------------
 140 Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 141 ---------------------------------------------------------------------------------
 142
 143 Report RTL Partitions:
 144 +-+--------------+------------+----------+
 145 | |RTL Partition |Replication |Instances |
 146 +-+--------------+------------+----------+
 147 +-+--------------+------------+----------+
 148 ---------------------------------------------------------------------------------
 149 Start Rebuilding User Hierarchy
 150 ---------------------------------------------------------------------------------
 151 ---------------------------------------------------------------------------------
 152 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 153 ---------------------------------------------------------------------------------
 154 ---------------------------------------------------------------------------------
 155 Start Renaming Generated Ports
 156 ---------------------------------------------------------------------------------
 157 ---------------------------------------------------------------------------------
 158 Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 159 ---------------------------------------------------------------------------------
 160 ---------------------------------------------------------------------------------
 161 Start Handling Custom Attributes
 162 ---------------------------------------------------------------------------------
 163 ---------------------------------------------------------------------------------
 164 Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 165 ---------------------------------------------------------------------------------
 166 ---------------------------------------------------------------------------------
 167 Start Renaming Generated Nets
 168 ---------------------------------------------------------------------------------
 169 ---------------------------------------------------------------------------------
 170 Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 171 ---------------------------------------------------------------------------------
 172 ---------------------------------------------------------------------------------
 173 Start Writing Synthesis Report
 174 ---------------------------------------------------------------------------------
 175
 176 Report BlackBoxes:
 177 +-+--------------+----------+
 178 | |BlackBox name |Instances |
 179 +-+--------------+----------+
 180 +-+--------------+----------+
 181
 182 Report Cell Usage:
 183 +------+-------------+------+
 184 |      |Cell         |Count |
 185 +------+-------------+------+
 186 |1     |esdi_ctl_phy |     1|
 187 +------+-------------+------+
 188
 189 Report Instance Areas:
 190 +------+---------+-------+------+
 191 |      |Instance |Module |Cells |
 192 +------+---------+-------+------+
 193 |1     |top      |       |     0|
 194 +------+---------+-------+------+
 195 ---------------------------------------------------------------------------------
 196 Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 197 ---------------------------------------------------------------------------------
 198 Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
 199 Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 200 Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 201 INFO: [Project 1-571] Translating synthesized netlist
 202 INFO: [Project 1-570] Preparing netlist for logic optimization
 203 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 204 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
 205 INFO: [Project 1-111] Unisim Transformation Summary:
 206 No Unisim elements were transformed.
 207
 208 INFO: [Common 17-83] Releasing license: Synthesis
 209 9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
 210 synth_design completed successfully
 211 synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191
 212 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
 213 WARNING: [Constraints 18-5210] No constraints selected for write.
 214 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 215 INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated.
 216 INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb
 217 INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019...