From 629d050f19bb3f76ee7dc79a7e45bc62f1ca73f3 Mon Sep 17 00:00:00 2001 From: Ian Sutton Date: Tue, 13 Aug 2019 13:22:17 -0500 Subject: [PATCH 1/1] initial --- esdi.cache/wt/gui_handlers.wdf | 50 ++++ esdi.cache/wt/java_command_handlers.wdf | 11 + esdi.cache/wt/project.wpc | 3 + esdi.cache/wt/synthesis.wdf | 39 +++ esdi.cache/wt/synthesis_details.wdf | 3 + esdi.cache/wt/webtalk_pa.xml | 82 ++++++ esdi.hw/esdi.lpr | 8 + esdi.hw/hw_1/hw.xml | 15 + esdi.ip_user_files/README.txt | 1 + esdi.runs/.jobs/vrs_config_1.xml | 8 + esdi.runs/.jobs/vrs_config_2.xml | 8 + .../impl_1/.Vivado_Implementation.queue.rst | 0 esdi.runs/impl_1/.init_design.begin.rst | 5 + esdi.runs/impl_1/.init_design.end.rst | 0 esdi.runs/impl_1/.opt_design.begin.rst | 5 + esdi.runs/impl_1/.opt_design.end.rst | 0 esdi.runs/impl_1/.place_design.begin.rst | 5 + esdi.runs/impl_1/.place_design.error.rst | 0 esdi.runs/impl_1/.vivado.begin.rst | 5 + esdi.runs/impl_1/.vivado.error.rst | 0 esdi.runs/impl_1/ISEWrap.js | 270 ++++++++++++++++++ esdi.runs/impl_1/ISEWrap.sh | 67 +++++ esdi.runs/impl_1/esdi_ctl_phy.tcl | 153 ++++++++++ esdi.runs/impl_1/esdi_ctl_phy.vdi | 174 +++++++++++ esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb | Bin 0 -> 37 bytes esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt | 41 +++ esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpx | Bin 0 -> 354 bytes esdi.runs/impl_1/esdi_ctl_phy_opt.dcp | Bin 0 -> 4220 bytes esdi.runs/impl_1/gen_run.xml | 121 ++++++++ esdi.runs/impl_1/htr.txt | 9 + esdi.runs/impl_1/init_design.pb | Bin 0 -> 1622 bytes esdi.runs/impl_1/opt_design.pb | Bin 0 -> 10826 bytes esdi.runs/impl_1/place_design.pb | Bin 0 -> 3231 bytes esdi.runs/impl_1/project.wdf | 31 ++ esdi.runs/impl_1/rundef.js | 40 +++ esdi.runs/impl_1/runme.bat | 10 + esdi.runs/impl_1/runme.log | 173 +++++++++++ esdi.runs/impl_1/runme.sh | 47 +++ esdi.runs/impl_1/vivado.jou | 12 + esdi.runs/impl_1/vivado.pb | 4 + esdi.runs/synth_1/.Vivado_Synthesis.queue.rst | 0 esdi.runs/synth_1/.vivado.begin.rst | 5 + esdi.runs/synth_1/.vivado.end.rst | 0 esdi.runs/synth_1/ISEWrap.js | 270 ++++++++++++++++++ esdi.runs/synth_1/ISEWrap.sh | 67 +++++ esdi.runs/synth_1/__synthesis_is_complete__ | 0 esdi.runs/synth_1/esdi_ctl_phy.dcp | Bin 0 -> 3830 bytes esdi.runs/synth_1/esdi_ctl_phy.tcl | 53 ++++ esdi.runs/synth_1/esdi_ctl_phy.vds | 218 ++++++++++++++ .../synth_1/esdi_ctl_phy_utilization_synth.pb | Bin 0 -> 224 bytes .../esdi_ctl_phy_utilization_synth.rpt | 187 ++++++++++++ esdi.runs/synth_1/gen_run.xml | 53 ++++ esdi.runs/synth_1/htr.txt | 9 + esdi.runs/synth_1/project.wdf | 31 ++ esdi.runs/synth_1/rundef.js | 36 +++ esdi.runs/synth_1/runme.bat | 10 + esdi.runs/synth_1/runme.log | 217 ++++++++++++++ esdi.runs/synth_1/runme.sh | 43 +++ esdi.runs/synth_1/vivado.jou | 12 + esdi.runs/synth_1/vivado.pb | Bin 0 -> 21879 bytes esdi.srcs/sources_1/new/esdi_data_phy.v | 34 +++ esdi.srcs/sources_1/new/esdi_phy_ctl.v | 42 +++ esdi.xpr | 218 ++++++++++++++ 63 files changed, 2905 insertions(+) create mode 100644 esdi.cache/wt/gui_handlers.wdf create mode 100644 esdi.cache/wt/java_command_handlers.wdf create mode 100644 esdi.cache/wt/project.wpc create mode 100644 esdi.cache/wt/synthesis.wdf create mode 100644 esdi.cache/wt/synthesis_details.wdf create mode 100644 esdi.cache/wt/webtalk_pa.xml create mode 100644 esdi.hw/esdi.lpr create mode 100644 esdi.hw/hw_1/hw.xml create mode 100644 esdi.ip_user_files/README.txt create mode 100644 esdi.runs/.jobs/vrs_config_1.xml create mode 100644 esdi.runs/.jobs/vrs_config_2.xml create mode 100644 esdi.runs/impl_1/.Vivado_Implementation.queue.rst create mode 100644 esdi.runs/impl_1/.init_design.begin.rst create mode 100644 esdi.runs/impl_1/.init_design.end.rst create mode 100644 esdi.runs/impl_1/.opt_design.begin.rst create mode 100644 esdi.runs/impl_1/.opt_design.end.rst create mode 100644 esdi.runs/impl_1/.place_design.begin.rst create mode 100644 esdi.runs/impl_1/.place_design.error.rst create mode 100644 esdi.runs/impl_1/.vivado.begin.rst create mode 100644 esdi.runs/impl_1/.vivado.error.rst create mode 100644 esdi.runs/impl_1/ISEWrap.js create mode 100644 esdi.runs/impl_1/ISEWrap.sh create mode 100644 esdi.runs/impl_1/esdi_ctl_phy.tcl create mode 100644 esdi.runs/impl_1/esdi_ctl_phy.vdi create mode 100644 esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb create mode 100644 esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt create mode 100644 esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpx create mode 100644 esdi.runs/impl_1/esdi_ctl_phy_opt.dcp create mode 100644 esdi.runs/impl_1/gen_run.xml create mode 100644 esdi.runs/impl_1/htr.txt create mode 100644 esdi.runs/impl_1/init_design.pb create mode 100644 esdi.runs/impl_1/opt_design.pb create mode 100644 esdi.runs/impl_1/place_design.pb create mode 100644 esdi.runs/impl_1/project.wdf create mode 100644 esdi.runs/impl_1/rundef.js create mode 100644 esdi.runs/impl_1/runme.bat create mode 100644 esdi.runs/impl_1/runme.log create mode 100644 esdi.runs/impl_1/runme.sh create mode 100644 esdi.runs/impl_1/vivado.jou create mode 100644 esdi.runs/impl_1/vivado.pb create mode 100644 esdi.runs/synth_1/.Vivado_Synthesis.queue.rst create mode 100644 esdi.runs/synth_1/.vivado.begin.rst create mode 100644 esdi.runs/synth_1/.vivado.end.rst create mode 100644 esdi.runs/synth_1/ISEWrap.js create mode 100644 esdi.runs/synth_1/ISEWrap.sh create mode 100644 esdi.runs/synth_1/__synthesis_is_complete__ create mode 100644 esdi.runs/synth_1/esdi_ctl_phy.dcp create mode 100644 esdi.runs/synth_1/esdi_ctl_phy.tcl create mode 100644 esdi.runs/synth_1/esdi_ctl_phy.vds create mode 100644 esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb create mode 100644 esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt create mode 100644 esdi.runs/synth_1/gen_run.xml create mode 100644 esdi.runs/synth_1/htr.txt create mode 100644 esdi.runs/synth_1/project.wdf create mode 100644 esdi.runs/synth_1/rundef.js create mode 100644 esdi.runs/synth_1/runme.bat create mode 100644 esdi.runs/synth_1/runme.log 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+73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3337342e3231314d42:00:00 +eof:776646770 diff --git a/esdi.cache/wt/synthesis_details.wdf b/esdi.cache/wt/synthesis_details.wdf new file mode 100644 index 0000000..227096f --- /dev/null +++ b/esdi.cache/wt/synthesis_details.wdf @@ -0,0 +1,3 @@ +version:1 +73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00 +eof:2511430288 diff --git a/esdi.cache/wt/webtalk_pa.xml b/esdi.cache/wt/webtalk_pa.xml new file mode 100644 index 0000000..7985efd --- /dev/null +++ b/esdi.cache/wt/webtalk_pa.xml @@ -0,0 +1,82 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/esdi.hw/esdi.lpr b/esdi.hw/esdi.lpr new file mode 100644 index 0000000..8d9c70d --- /dev/null +++ b/esdi.hw/esdi.lpr @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/esdi.hw/hw_1/hw.xml b/esdi.hw/hw_1/hw.xml new file mode 100644 index 0000000..cd0a367 --- /dev/null +++ b/esdi.hw/hw_1/hw.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/esdi.ip_user_files/README.txt b/esdi.ip_user_files/README.txt new file mode 100644 index 0000000..9015e04 --- /dev/null +++ b/esdi.ip_user_files/README.txt @@ -0,0 +1 @@ +The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. diff --git a/esdi.runs/.jobs/vrs_config_1.xml b/esdi.runs/.jobs/vrs_config_1.xml new file mode 100644 index 0000000..afd27fb --- /dev/null +++ b/esdi.runs/.jobs/vrs_config_1.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/esdi.runs/.jobs/vrs_config_2.xml b/esdi.runs/.jobs/vrs_config_2.xml new file mode 100644 index 0000000..897bfb4 --- /dev/null +++ b/esdi.runs/.jobs/vrs_config_2.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/esdi.runs/impl_1/.Vivado_Implementation.queue.rst b/esdi.runs/impl_1/.Vivado_Implementation.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/impl_1/.init_design.begin.rst b/esdi.runs/impl_1/.init_design.begin.rst new file mode 100644 index 0000000..1e7d57c --- /dev/null +++ b/esdi.runs/impl_1/.init_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/esdi.runs/impl_1/.init_design.end.rst b/esdi.runs/impl_1/.init_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/impl_1/.opt_design.begin.rst b/esdi.runs/impl_1/.opt_design.begin.rst new file mode 100644 index 0000000..1e7d57c --- /dev/null +++ b/esdi.runs/impl_1/.opt_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/esdi.runs/impl_1/.opt_design.end.rst b/esdi.runs/impl_1/.opt_design.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/impl_1/.place_design.begin.rst b/esdi.runs/impl_1/.place_design.begin.rst new file mode 100644 index 0000000..1e7d57c --- /dev/null +++ b/esdi.runs/impl_1/.place_design.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/esdi.runs/impl_1/.place_design.error.rst b/esdi.runs/impl_1/.place_design.error.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/impl_1/.vivado.begin.rst b/esdi.runs/impl_1/.vivado.begin.rst new file mode 100644 index 0000000..b16ec11 --- /dev/null +++ b/esdi.runs/impl_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/esdi.runs/impl_1/.vivado.error.rst b/esdi.runs/impl_1/.vivado.error.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/impl_1/ISEWrap.js b/esdi.runs/impl_1/ISEWrap.js new file mode 100644 index 0000000..3e83de1 --- /dev/null +++ b/esdi.runs/impl_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/esdi.runs/impl_1/ISEWrap.sh b/esdi.runs/impl_1/ISEWrap.sh new file mode 100644 index 0000000..f679f2e --- /dev/null +++ b/esdi.runs/impl_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/esdi.runs/impl_1/esdi_ctl_phy.tcl b/esdi.runs/impl_1/esdi_ctl_phy.tcl new file mode 100644 index 0000000..1464cec --- /dev/null +++ b/esdi.runs/impl_1/esdi_ctl_phy.tcl @@ -0,0 +1,153 @@ +# +# Report generation script generated by Vivado +# + +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +proc start_step { step } { + set stopFile ".stop.rst" + if {[file isfile .stop.rst]} { + puts "" + puts "*** Halting run - EA reset detected ***" + puts "" + puts "" + return -code error + } + set beginFile ".$step.begin.rst" + set platform "$::tcl_platform(platform)" + set user "$::tcl_platform(user)" + set pid [pid] + set host "" + if { [string equal $platform unix] } { + if { [info exist ::env(HOSTNAME)] } { + set host $::env(HOSTNAME) + } + } else { + if { [info exist ::env(COMPUTERNAME)] } { + set host $::env(COMPUTERNAME) + } + } + set ch [open $beginFile w] + puts $ch "" + puts $ch "" + puts $ch " " + puts $ch " " + puts $ch "" + close $ch +} + +proc end_step { step } { + set endFile ".$step.end.rst" + set ch [open $endFile w] + close $ch +} + +proc step_failed { step } { + set endFile ".$step.error.rst" + set ch [open $endFile w] + close $ch +} + + +start_step init_design +set ACTIVE_STEP init_design +set rc [catch { + create_msg_db init_design.pb + set_param chipscope.maxJobs 6 + create_project -in_memory -part xc7z007sclg225-1 + set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project] + set_property board_part em.avnet.com:minized:part0:1.2 [current_project] + set_property design_mode GateLvl [current_fileset] + set_param project.singleFileAddWarning.threshold 0 + set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project] + set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project] + set_property ip_output_repo S:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project] + set_property ip_cache_permissions {read write} [current_project] + add_files -quiet S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp + link_design -top esdi_ctl_phy -part xc7z007sclg225-1 + close_msg_db -file init_design.pb +} RESULT] +if {$rc} { + step_failed init_design + return -code error $RESULT +} else { + end_step init_design + unset ACTIVE_STEP +} + +start_step opt_design +set ACTIVE_STEP opt_design +set rc [catch { + create_msg_db opt_design.pb + opt_design + write_checkpoint -force esdi_ctl_phy_opt.dcp + create_report "impl_1_opt_report_drc_0" "report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx" + close_msg_db -file opt_design.pb +} RESULT] +if {$rc} { + step_failed opt_design + return -code error $RESULT +} else { + end_step opt_design + unset ACTIVE_STEP +} + +start_step place_design +set ACTIVE_STEP place_design +set rc [catch { + create_msg_db place_design.pb + if { [llength [get_debug_cores -quiet] ] > 0 } { + implement_debug_core + } + place_design + write_checkpoint -force esdi_ctl_phy_placed.dcp + create_report "impl_1_place_report_io_0" "report_io -file esdi_ctl_phy_io_placed.rpt" + create_report "impl_1_place_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_placed.rpt -pb esdi_ctl_phy_utilization_placed.pb" + create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file esdi_ctl_phy_control_sets_placed.rpt" + close_msg_db -file place_design.pb +} RESULT] +if {$rc} { + step_failed place_design + return -code error $RESULT +} else { + end_step place_design + unset ACTIVE_STEP +} + +start_step route_design +set ACTIVE_STEP route_design +set rc [catch { + create_msg_db route_design.pb + route_design + write_checkpoint -force esdi_ctl_phy_routed.dcp + create_report "impl_1_route_report_drc_0" "report_drc -file esdi_ctl_phy_drc_routed.rpt -pb esdi_ctl_phy_drc_routed.pb -rpx esdi_ctl_phy_drc_routed.rpx" + create_report "impl_1_route_report_methodology_0" "report_methodology -file esdi_ctl_phy_methodology_drc_routed.rpt -pb esdi_ctl_phy_methodology_drc_routed.pb -rpx esdi_ctl_phy_methodology_drc_routed.rpx" + create_report "impl_1_route_report_power_0" "report_power -file esdi_ctl_phy_power_routed.rpt -pb esdi_ctl_phy_power_summary_routed.pb -rpx esdi_ctl_phy_power_routed.rpx" + create_report "impl_1_route_report_route_status_0" "report_route_status -file esdi_ctl_phy_route_status.rpt -pb esdi_ctl_phy_route_status.pb" + create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file esdi_ctl_phy_timing_summary_routed.rpt -pb esdi_ctl_phy_timing_summary_routed.pb -rpx esdi_ctl_phy_timing_summary_routed.rpx -warn_on_violation " + create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file esdi_ctl_phy_incremental_reuse_routed.rpt" + create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file esdi_ctl_phy_clock_utilization_routed.rpt" + create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file esdi_ctl_phy_bus_skew_routed.rpt -pb esdi_ctl_phy_bus_skew_routed.pb -rpx esdi_ctl_phy_bus_skew_routed.rpx" + close_msg_db -file route_design.pb +} RESULT] +if {$rc} { + write_checkpoint -force esdi_ctl_phy_routed_error.dcp + step_failed route_design + return -code error $RESULT +} else { + end_step route_design + unset ACTIVE_STEP +} + diff --git a/esdi.runs/impl_1/esdi_ctl_phy.vdi b/esdi.runs/impl_1/esdi_ctl_phy.vdi new file mode 100644 index 0000000..389a74a --- /dev/null +++ b/esdi.runs/impl_1/esdi_ctl_phy.vdi @@ -0,0 +1,174 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Tue Aug 13 10:39:28 2019 +# Process ID: 13936 +# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1 +# Command line: vivado.exe -log esdi_ctl_phy.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace +# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy.vdi +# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source esdi_ctl_phy.tcl -notrace +Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7z007sclg225-1 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx +Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000 +ERROR: [Place 30-494] The design is empty +Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. +Ending Placer Task | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. +place_design failed +ERROR: [Common 17-69] Command failed: Placer could not place all instances +INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019... diff --git a/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb new file mode 100644 index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40 GIT binary patch literal 37 scmd;LGcqtV(KDRH% + Ruledeck: default + Max violations: + Violations found: 1 ++--------+----------+--------------------+------------+ +| Rule | Severity | Description | Violations | ++--------+----------+--------------------+------------+ +| ZPS7-1 | Warning | PS7 block required | 1 | ++--------+----------+--------------------+------------+ + +2. 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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3766626462656662353231383438653961626661396637663131336536353232:506172656e742050412070726f6a656374204944:00 +eof:3165293120 diff --git a/esdi.runs/impl_1/rundef.js b/esdi.runs/impl_1/rundef.js new file mode 100644 index 0000000..e169657 --- /dev/null +++ b/esdi.runs/impl_1/rundef.js @@ -0,0 +1,40 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;"; +} else { + PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +// pre-commands: +ISETouchFile( "init_design", "begin" ); +ISEStep( "vivado", + "-log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace" ); + + + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/esdi.runs/impl_1/runme.bat b/esdi.runs/impl_1/runme.bat new file mode 100644 index 0000000..bc78723 --- /dev/null +++ b/esdi.runs/impl_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/esdi.runs/impl_1/runme.log b/esdi.runs/impl_1/runme.log new file mode 100644 index 0000000..15952e6 --- /dev/null +++ b/esdi.runs/impl_1/runme.log @@ -0,0 +1,173 @@ + +*** Running vivado + with args -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source esdi_ctl_phy.tcl -notrace +Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1 +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +INFO: [Device 21-403] Loading part xc7z007sclg225-1 +INFO: [Project 1-479] Netlist was created with Vivado 2019.1 +INFO: [Project 1-570] Preparing netlist for logic optimization +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +link_design completed successfully +link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582 +Command: opt_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' +Running DRC as a precondition to command opt_design + +Starting DRC Task +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Project 1-461] DRC finished with 0 Errors +INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. + +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824 + +Starting Cache Timing Information Task +INFO: [Timing 38-35] Done setting XDC timing constraints. +Ending Cache Timing Information Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363 + +Starting Logic Optimization Task + +Phase 1 Retarget +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +INFO: [Opt 31-49] Retargeted 0 cell(s). +Phase 1 Retarget | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells + +Phase 2 Constant propagation +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Phase 2 Constant propagation | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells + +Phase 3 Sweep +Phase 3 Sweep | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells + +Phase 4 BUFG optimization +Phase 4 BUFG optimization | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. + +Phase 5 Shift Register Optimization +INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs +Phase 5 Shift Register Optimization | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells + +Phase 6 Post Processing Netlist +Phase 6 Post Processing Netlist | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781 +INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells +Opt_design Change Summary +========================= + + +------------------------------------------------------------------------------------------------------------------------- +| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | +------------------------------------------------------------------------------------------------------------------------- +| Retarget | 0 | 0 | 0 | +| Constant propagation | 0 | 0 | 0 | +| Sweep | 0 | 0 | 0 | +| BUFG optimization | 0 | 0 | 0 | +| Shift Register Optimization | 0 | 0 | 0 | +| Post Processing Netlist | 0 | 0 | 0 | +------------------------------------------------------------------------------------------------------------------------- + + + +Starting Connectivity Check Task + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +Ending Logic Optimization Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781 + +Starting Power Optimization Task +INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. +Ending Power Optimization Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000 + +Starting Final Cleanup Task +Ending Final Cleanup Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000 + +Starting Netlist Obfuscation Task +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +Ending Netlist Obfuscation Task | Checksum: 686e1c75 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +opt_design completed successfully +opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated. +INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx +Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'. +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt. +report_drc completed successfully +Command: place_design +Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s' +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. +Running DRC as a precondition to command place_design +INFO: [DRC 23-27] Running DRC with 2 threads +INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors +INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. + +Starting Placer Task +INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs + +Phase 1 Placer Initialization + +Phase 1.1 Placer Initialization Netlist Sorting +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000 +Phase 1 Placer Initialization | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000 +ERROR: [Place 30-494] The design is empty +Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports. +Ending Placer Task | Checksum: 00000000 + +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000 +INFO: [Common 17-83] Releasing license: Implementation +37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered. +place_design failed +ERROR: [Common 17-69] Command failed: Placer could not place all instances +INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019... diff --git a/esdi.runs/impl_1/runme.sh b/esdi.runs/impl_1/runme.sh new file mode 100644 index 0000000..6a4a4d5 --- /dev/null +++ b/esdi.runs/impl_1/runme.sh @@ -0,0 +1,47 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin +else + PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='S:/vivado-projects/esdi/esdi/esdi.runs/impl_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +# pre-commands: +/bin/touch .init_design.begin.rst +EAStep vivado -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace + + diff --git a/esdi.runs/impl_1/vivado.jou b/esdi.runs/impl_1/vivado.jou new file mode 100644 index 0000000..ff9b6ad --- /dev/null +++ b/esdi.runs/impl_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Tue Aug 13 10:39:28 2019 +# Process ID: 13936 +# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1 +# Command line: vivado.exe -log esdi_ctl_phy.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace +# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy.vdi +# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1\vivado.jou +#----------------------------------------------------------- +source esdi_ctl_phy.tcl -notrace diff --git a/esdi.runs/impl_1/vivado.pb b/esdi.runs/impl_1/vivado.pb new file mode 100644 index 0000000..b155e40 --- /dev/null +++ b/esdi.runs/impl_1/vivado.pb @@ -0,0 +1,4 @@ + + + +End Record \ No newline at end of file diff --git a/esdi.runs/synth_1/.Vivado_Synthesis.queue.rst b/esdi.runs/synth_1/.Vivado_Synthesis.queue.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/synth_1/.vivado.begin.rst b/esdi.runs/synth_1/.vivado.begin.rst new file mode 100644 index 0000000..c39ccbb --- /dev/null +++ b/esdi.runs/synth_1/.vivado.begin.rst @@ -0,0 +1,5 @@ + + + + + diff --git a/esdi.runs/synth_1/.vivado.end.rst b/esdi.runs/synth_1/.vivado.end.rst new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/synth_1/ISEWrap.js b/esdi.runs/synth_1/ISEWrap.js new file mode 100644 index 0000000..3e83de1 --- /dev/null +++ b/esdi.runs/synth_1/ISEWrap.js @@ -0,0 +1,270 @@ +// +// Vivado(TM) +// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6 +// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. +// + +// GLOBAL VARIABLES +var ISEShell = new ActiveXObject( "WScript.Shell" ); +var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" ); +var ISERunDir = ""; +var ISELogFile = "runme.log"; +var ISELogFileStr = null; +var ISELogEcho = true; +var ISEOldVersionWSH = false; + + + +// BOOTSTRAP +ISEInit(); + + + +// +// ISE FUNCTIONS +// +function ISEInit() { + + // 1. RUN DIR setup + var ISEScrFP = WScript.ScriptFullName; + var ISEScrN = WScript.ScriptName; + ISERunDir = + ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 ); + + // 2. LOG file setup + ISELogFileStr = ISEOpenFile( ISELogFile ); + + // 3. LOG echo? + var ISEScriptArgs = WScript.Arguments; + for ( var loopi=0; loopi> " + ISELogFile + " 2>&1"; + ISEExitCode = ISEShell.Run( ISECmdLine, 0, true ); + ISELogFileStr = ISEOpenFile( ISELogFile ); + + } else { // WSH 5.6 + + // LAUNCH! + ISEShell.CurrentDirectory = ISERunDir; + + // Redirect STDERR to STDOUT + ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1"; + var ISEProcess = ISEShell.Exec( ISECmdLine ); + + // BEGIN file creation + var wbemFlagReturnImmediately = 0x10; + var wbemFlagForwardOnly = 0x20; + var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2"); + var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly); + var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly); + var NOC = 0; + var NOLP = 0; + var TPM = 0; + + var cpuInfos = new Enumerator(processor); + for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) { + var cpuInfo = cpuInfos.item(); + NOC += cpuInfo.NumberOfCores; + NOLP += cpuInfo.NumberOfLogicalProcessors; + } + var csInfos = new Enumerator(computerSystem); + for(;!csInfos.atEnd(); csInfos.moveNext()) { + var csInfo = csInfos.item(); + TPM += csInfo.TotalPhysicalMemory; + } + + var ISEHOSTCORE = NOLP + var ISEMEMTOTAL = TPM + + var ISENetwork = WScript.CreateObject( "WScript.Network" ); + var ISEHost = ISENetwork.ComputerName; + var ISEUser = ISENetwork.UserName; + var ISEPid = ISEProcess.ProcessID; + var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( " " ); + ISEBeginFile.WriteLine( "" ); + ISEBeginFile.Close(); + + var ISEOutStr = ISEProcess.StdOut; + var ISEErrStr = ISEProcess.StdErr; + + // WAIT for ISEStep to finish + while ( ISEProcess.Status == 0 ) { + + // dump stdout then stderr - feels a little arbitrary + while ( !ISEOutStr.AtEndOfStream ) { + ISEStdOut( ISEOutStr.ReadLine() ); + } + + WScript.Sleep( 100 ); + } + + ISEExitCode = ISEProcess.ExitCode; + } + + ISELogFileStr.Close(); + + // END/ERROR file creation + if ( ISEExitCode != 0 ) { + ISETouchFile( ISEStep, "error" ); + + } else { + ISETouchFile( ISEStep, "end" ); + } + + return ISEExitCode; +} + + +// +// UTILITIES +// +function ISEStdOut( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdOut.WriteLine( ISELine ); + } +} + +function ISEStdErr( ISELine ) { + + ISELogFileStr.WriteLine( ISELine ); + + if ( ISELogEcho ) { + WScript.StdErr.WriteLine( ISELine ); + } +} + +function ISETouchFile( ISERoot, ISEStatus ) { + + var ISETFile = + ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" ); + ISETFile.Close(); +} + +function ISEOpenFile( ISEFilename ) { + + // This function has been updated to deal with a problem seen in CR #870871. + // In that case the user runs a script that runs impl_1, and then turns around + // and runs impl_1 -to_step write_bitstream. That second run takes place in + // the same directory, which means we may hit some of the same files, and in + // particular, we will open the runme.log file. Even though this script closes + // the file (now), we see cases where a subsequent attempt to open the file + // fails. Perhaps the OS is slow to release the lock, or the disk comes into + // play? In any case, we try to work around this by first waiting if the file + // is already there for an arbitrary 5 seconds. Then we use a try-catch block + // and try to open the file 10 times with a one second delay after each attempt. + // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871. + // If there is an unrecognized exception when trying to open the file, we output + // an error message and write details to an exception.log file. + var ISEFullPath = ISERunDir + "/" + ISEFilename; + if (ISEFileSys.FileExists(ISEFullPath)) { + // File is already there. This could be a problem. Wait in case it is still in use. + WScript.Sleep(5000); + } + var i; + for (i = 0; i < 10; ++i) { + try { + return ISEFileSys.OpenTextFile(ISEFullPath, 8, true); + } catch (exception) { + var error_code = exception.number & 0xFFFF; // The other bits are a facility code. + if (error_code == 52) { // 52 is bad file name or number. + // Wait a second and try again. + WScript.Sleep(1000); + continue; + } else { + WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + var exceptionFilePath = ISERunDir + "/exception.log"; + if (!ISEFileSys.FileExists(exceptionFilePath)) { + WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details."); + var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true); + exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath); + exceptionFile.WriteLine("\tException name: " + exception.name); + exceptionFile.WriteLine("\tException error code: " + error_code); + exceptionFile.WriteLine("\tException message: " + exception.message); + exceptionFile.Close(); + } + throw exception; + } + } + } + // If we reached this point, we failed to open the file after 10 attempts. + // We need to error out. + WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath); + WScript.Quit(1); +} diff --git a/esdi.runs/synth_1/ISEWrap.sh b/esdi.runs/synth_1/ISEWrap.sh new file mode 100644 index 0000000..f679f2e --- /dev/null +++ b/esdi.runs/synth_1/ISEWrap.sh @@ -0,0 +1,67 @@ +#!/bin/sh + +# +# Vivado(TM) +# ISEWrap.sh: Vivado Runs Script for UNIX +# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. +# + +HD_LOG=$1 +shift + +# CHECK for a STOP FILE +if [ -f .stop.rst ] +then +echo "" >> $HD_LOG +echo "*** Halting run - EA reset detected ***" >> $HD_LOG +echo "" >> $HD_LOG +exit 1 +fi + +ISE_STEP=$1 +shift + +# WRITE STEP HEADER to LOG +echo "" >> $HD_LOG +echo "*** Running $ISE_STEP" >> $HD_LOG +echo " with args $@" >> $HD_LOG +echo "" >> $HD_LOG + +# LAUNCH! +$ISE_STEP "$@" >> $HD_LOG 2>&1 & + +# BEGIN file creation +ISE_PID=$! +if [ X != X$HOSTNAME ] +then +ISE_HOST=$HOSTNAME #bash +else +ISE_HOST=$HOST #csh +fi +ISE_USER=$USER + +ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l) +ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo) + +ISE_BEGINFILE=.$ISE_STEP.begin.rst +/bin/touch $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo " " >> $ISE_BEGINFILE +echo "" >> $ISE_BEGINFILE + +# WAIT for ISEStep to finish +wait $ISE_PID + +# END/ERROR file creation +RETVAL=$? +if [ $RETVAL -eq 0 ] +then + /bin/touch .$ISE_STEP.end.rst +else + /bin/touch .$ISE_STEP.error.rst +fi + +exit $RETVAL + diff --git a/esdi.runs/synth_1/__synthesis_is_complete__ b/esdi.runs/synth_1/__synthesis_is_complete__ new file mode 100644 index 0000000..e69de29 diff --git a/esdi.runs/synth_1/esdi_ctl_phy.dcp b/esdi.runs/synth_1/esdi_ctl_phy.dcp new file mode 100644 index 0000000000000000000000000000000000000000..b783168dd52d6da016f4a561b5a21461e93fd0ae GIT binary patch literal 3830 zcmZ{n1yEFL8^;$Aq`PAgC8d^brD2yw2~lF{SjrVpL=;y*N@0~Q=?;lSk(O}j7Fbe1 zKw@cB>RY~hXYRQ7``(#%&Y3gk_dM^+|EbqlkLVI3001BbEZ?Rw>KQHAjwAp8QiuS6 z%eb$O4nATJJz+6#OpHoEtg4yVV6D$1jWqT=^H(RG9cSLYphAGK9BZz=F@s1`pS`bh zYd_2wvKtQ5GEhO#`?VF2L6b>PYeATk`l7pRN^gMl(_-R9a@d&^1|ZxSn#Mku6ccQ4 zB28+7GPF3mO5$;Es0jM0oXQ#_|8%)WnzC9BJaT+_zOIy4)kD>%@-1cQHo*jSCFj7$ zeNK*2V?vm#b%tbs?~CC_*&H0>(5tFP-3AmVO+Ni7{nMfA36RIfK_`R@AJ9EI82^FN zH}e!CXn`nm{w;YkXR+%Q_GyjA-^O&PReDATbTv=CSE5P# z%hQDOWMKB=% z@Qxe+pvB4M1b1|^b$9@?^>KY9=H%$yXl?*c1<^JhTWt79+~6hoX84WsO>6>nCmRO6 zlphCebyqd!c{*ro3zmP+5D@4_c9~XqvuUP)ScQWjfpDDc+WTH`t$QE!hl+5@~?zZKHRqz_q|(x@U_K{7Kve5FLPLOxC5 z!}Wm`v7V9?FDRu(QJFCj#-B%g=mAXdR|qHzxx{&nU$yhcOEPoKER_5;1m2gn zRs*G*fR8{Q@3Iy)9SBr75uMJMQZcA_vk0zHZy^Q)RP)4H2U=2WY2^6hrQ)Y(qMcMm zVO(A-wJ+D9*5z8!GQQ!Qb)DrON7FLA^}7)n=qrwTYFb2*r7Q=*-Nnvii%jBsk{&JJ z*X<*|QQzuJ9+ghoHRDTK!J^7!(D~{=f9RZveDKT>B4qQrDKf@iExpSE1=(&S7I#GJ zF$%@d*%-JRL3p5{(mXQX+e^e+43ms+uLkA6jtcM6cs8!~mWh0_1(-{&-QLRSnpB!qoQWsduj?YU5 zpPVT)f4#~>7GIk|DRJN0^>0GGD{!!6~g-^tswC=ZKX8v}JlW-{?tEU~C zol2>xRMy`$T2Nq)wc+-#qPi1NH=^}sva%UUw9$VFFb(YO4 z79BukPYt)8Ukh(0%Nx1EWOjV;{Zo|qQ-yvfu9f7KCkmJ-WzpndqCaDGu(n^*6c?k> zxJ`#2t8QKn_bJf5eZ6|G1HdBS=zt#a$fI68F-V_5pD?)Bw+AgQt|uxvDkUdrDrhL$ zt>23-g@~Yg2db+eB9Q(sB6?;ZX)};90D7g3B*x?+>#$%f1>nyElt@ZsU(_}>T*CY- zS?)VR4Psl}F{-p-sWr69@j}*=p2VV$S7kaRUZ{HUYbTByUafs$8fl3&%ngk<--zZc zzz(mhrS2=#BZZb~luo41<<3hPOCRzQi#vb(YAr%a}8tpAw3Z*U-ghlg&{I6*wmBm=u|4eNx3 z^?9aBXvBL084OpX%No`pNoA%67K<3;wP}69zI>04Gh%T>YKQq!$9ej)qK^96H{lW; zK1qv?zQQ2w4HAgsIP+)4Pr&O0;D&Ejn^I%HGrF=EovrA+lwBI(9L9WmeZ=la-UpDWp93DvI z1$ZAF9IRm_Q%vz6YhMNDC|-H>PwEnrl`if7yBkiOASZrLx?N(CvsvVFG8HE|nB z+^pO3v3G9{j0v_Z*|hQ1Q^EC!g-a46FYQ+csbKeyF_{}bHxrRD;mNAAky=?wRBh`d zGXiZj*=hV^_wyK$SqJ+~i-g}DevMpa3pL=2Fk^@ci;m7yE_Yku6`1z-$gL3TDz}m2 zeVyUv^ojG#T)Xpk@=1YJRefYriNt%3>^shrM^)x7^-&|mv0c43r{~2%sx7aucUpDB z`-KT(N{dP1Xv?rJf%pwigrvD#R@#z&M@Y!MGtJ6JmN|n+tT-`iieb@al#?%jD85zr zLxma1w;-q^?Fafk6!>?yOVHl&l%x%*YBcz^Sh^KWu(!Kzh}*KS|b7>J8}b=??9y>|wfT^z%%5?%jM ze9e{q0k%kkJE2yqj^BRjY$*f+I37^xmuCF1EQ&6bo1Cr`7)BX{40r=~g7O|7sUhZ= zAO*n%jD`BLugKztd!Xh&emGSltakq_V8(jyNPTeyOdU6zG2lhAE&PF>y_mnBshSrC zMBA{=1cw2}P@L~vV{Z-J@=`NqY^3A3??jgc4!y@Wj@3i^YY}W|wNM5)2ars8?MUrA z)Px%jDhHh(`Zaq1x4RVAjbt(!X6M7<50gpgZRCAV?5c~3H<_CiQ(L-hv^f!MoQorn z@Ee*T&`m+)#Qf0INv@l2TCBD>SAob|+Ufn!15q7X8?H6EhA@UH+MWG|WPfF){PtBL zvTMQ?o#QSF3vxQ^Z3IG;CVP*p{jWGUcSH+?oM=vh!CR6IMPi9?Npm;fVr-{4*Bg_F z^r@pG8SZ@gi?(f6yX=#21B zh2#h*oQ-e_L2(K(|8Ip{9butJHKR6F+EDB%6MR&YR7>MU1}VLUdbS$PtSn}$X2vpL zeS>kWIRHZ>^kLq!dTu?n?uit8YxlV5TDIfMmDkln59kLLG%Th#x9l9MBt%Nc{nJ}o zskw%MWAeohAV{l;(y!~h?wp4OJDB4)6HUtA=2u_2&@3+dr)tu%k53aS=4o}t7xpmM zL;-9>C8nRBk=hg(j9Sh>Ok83IXH43SWy6kh~=_F#2D3Q zM#}eh@?IcC28zP#PG<|>tA+#8d^Jd4r82_KT;2!W$sOr5@++frTh?PL+6=aH z_Y588B|_6hO}Ui$Syb;0GHQ$!#br(o*tCFwo6m|`c_Hry^P@5~n~n7daHakK-(he% z0C1WBP$3s@f8S{EA^b`D;@7{R3f$w5o`IXI@oD_o<{$d*B|Q3K(!s~^CzA{OVxdB& z@p0Uof=}c3#|!eWqrWA=bB^nl_%wcdyr3@@Dr5woe&~e{<5#2$@GsZtWPiH;yFTF? zz)zTe4BVvnp9XO0W2{GvJK4pJl@zdz^VUWQ0Ehv!q&>iX5`HEwn!f6{94zgf&0$Ut e6tuk!;nF@X?vGqFAto>bh_rX0r@B>u%6|aBVt2d% literal 0 HcmV?d00001 diff --git a/esdi.runs/synth_1/esdi_ctl_phy.tcl b/esdi.runs/synth_1/esdi_ctl_phy.tcl new file mode 100644 index 0000000..d9a824d --- /dev/null +++ b/esdi.runs/synth_1/esdi_ctl_phy.tcl @@ -0,0 +1,53 @@ +# +# Synthesis run script generated by Vivado +# + +set TIME_start [clock seconds] +proc create_report { reportName command } { + set status "." + append status $reportName ".fail" + if { [file exists $status] } { + eval file delete [glob $status] + } + send_msg_id runtcl-4 info "Executing : $command" + set retval [eval catch { $command } msg] + if { $retval != 0 } { + set fp [open $status w] + close $fp + send_msg_id runtcl-5 warning "$msg" + } +} +create_project -in_memory -part xc7z007sclg225-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project] +set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language Verilog [current_project] +set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project] +set_property board_part em.avnet.com:minized:part0:1.2 [current_project] +set_property ip_output_repo s:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_verilog -library xil_defaultlib S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp +} +set_param ips.enableIPCacheLiteLoad 1 +close [open __synthesis_is_running__ w] + +synth_design -top esdi_ctl_phy -part xc7z007sclg225-1 + + +# disable binary constraint mode for synth run checkpoints +set_param constraints.enableBinaryConstraints false +write_checkpoint -force -noxdef esdi_ctl_phy.dcp +create_report "synth_1_synth_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb" +file delete __synthesis_is_running__ +close [open __synthesis_is_complete__ w] diff --git a/esdi.runs/synth_1/esdi_ctl_phy.vds b/esdi.runs/synth_1/esdi_ctl_phy.vds new file mode 100644 index 0000000..4dc8027 --- /dev/null +++ b/esdi.runs/synth_1/esdi_ctl_phy.vds @@ -0,0 +1,218 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Tue Aug 13 10:38:50 2019 +# Process ID: 20424 +# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1 +# Command line: vivado.exe -log esdi_ctl_phy.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl +# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.vds +# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source esdi_ctl_phy.tcl -notrace +Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 18332 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23] +WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z007sclg225-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z007sclg225-1 +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 66 (col length:40) +BRAMs: 100 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------------+------+ +| |Cell |Count | ++------+-------------+------+ +|1 |esdi_ctl_phy | 1| ++------+-------------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 0| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019... diff --git a/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb new file mode 100644 index 0000000000000000000000000000000000000000..8926a67112a9b54d6786bddf75b55035aa465d37 GIT binary patch literal 224 zcmd;LGcqu=)H9sKtPxzAo10ivsgR$hP+F3ilUbEml9`_e;%28-Dioy_=a&{Grxxp- z>~>u$1!Aw22a$h)WQ5aE z1rYnJDu|q`#=zj=^b|+}bs2%kyFjwVX{j-Yz19Lm{soavM=e3@Nmd+Ap>FQZAwfQ8 c?LY!^?SX{DQxM7U)&)fFbp;X*t!^MT0MP6*@&Et; literal 0 HcmV?d00001 diff --git a/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt new file mode 100644 index 0000000..3323731 --- /dev/null +++ b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt @@ -0,0 +1,187 @@ +Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +------------------------------------------------------------------------------------------------------------------- +| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019 +| Date : Tue Aug 13 10:39:11 2019 +| Host : KREMLINMACHINE running 64-bit major release (build 9200) +| Command : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb +| Design : esdi_ctl_phy +| Device : 7z007sclg225-1 +| Design State : Fully Placed +------------------------------------------------------------------------------------------------------------------- + +Utilization Design Information + +Table of Contents +----------------- +1. Slice Logic +1.1 Summary of Registers by Type +2. Slice Logic Distribution +3. Memory +4. DSP +5. IO and GT Specific +6. Clocking +7. Specific Feature +8. Primitives +9. Black Boxes +10. Instantiated Netlists + +1. Slice Logic +-------------- + ++-------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------------------+------+-------+-----------+-------+ +| Slice LUTs | 0 | 0 | 14400 | 0.00 | +| LUT as Logic | 0 | 0 | 14400 | 0.00 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| Slice Registers | 0 | 0 | 28800 | 0.00 | +| Register as Flip Flop | 0 | 0 | 28800 | 0.00 | +| Register as Latch | 0 | 0 | 28800 | 0.00 | +| F7 Muxes | 0 | 0 | 8800 | 0.00 | +| F8 Muxes | 0 | 0 | 4400 | 0.00 | ++-------------------------+------+-------+-----------+-------+ + + +1.1 Summary of Registers by Type +-------------------------------- + ++-------+--------------+-------------+--------------+ +| Total | Clock Enable | Synchronous | Asynchronous | ++-------+--------------+-------------+--------------+ +| 0 | _ | - | - | +| 0 | _ | - | Set | +| 0 | _ | - | Reset | +| 0 | _ | Set | - | +| 0 | _ | Reset | - | +| 0 | Yes | - | - | +| 0 | Yes | - | Set | +| 0 | Yes | - | Reset | +| 0 | Yes | Set | - | +| 0 | Yes | Reset | - | ++-------+--------------+-------------+--------------+ + + +2. Slice Logic Distribution +--------------------------- + ++------------------------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------------------------------------+------+-------+-----------+-------+ +| Slice | 0 | 0 | 4400 | 0.00 | +| SLICEL | 0 | 0 | | | +| SLICEM | 0 | 0 | | | +| LUT as Logic | 0 | 0 | 14400 | 0.00 | +| LUT as Memory | 0 | 0 | 6000 | 0.00 | +| LUT as Distributed RAM | 0 | 0 | | | +| LUT as Shift Register | 0 | 0 | | | +| Slice Registers | 0 | 0 | 28800 | 0.00 | +| Register driven from within the Slice | 0 | | | | +| Register driven from outside the Slice | 0 | | | | +| Unique Control Sets | 0 | | 4400 | 0.00 | ++------------------------------------------+------+-------+-----------+-------+ +* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets. + + +3. Memory +--------- + ++----------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++----------------+------+-------+-----------+-------+ +| Block RAM Tile | 0 | 0 | 50 | 0.00 | +| RAMB36/FIFO* | 0 | 0 | 50 | 0.00 | +| RAMB18 | 0 | 0 | 100 | 0.00 | ++----------------+------+-------+-----------+-------+ +* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1 + + +4. DSP +------ + ++-----------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------+------+-------+-----------+-------+ +| DSPs | 0 | 0 | 66 | 0.00 | ++-----------+------+-------+-----------+-------+ + + +5. IO and GT Specific +--------------------- + ++-----------------------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-----------------------------+------+-------+-----------+-------+ +| Bonded IOB | 0 | 0 | 54 | 0.00 | +| Bonded IPADs | 0 | 0 | 2 | 0.00 | +| Bonded IOPADs | 0 | 0 | 130 | 0.00 | +| PHY_CONTROL | 0 | 0 | 2 | 0.00 | +| PHASER_REF | 0 | 0 | 2 | 0.00 | +| OUT_FIFO | 0 | 0 | 8 | 0.00 | +| IN_FIFO | 0 | 0 | 8 | 0.00 | +| IDELAYCTRL | 0 | 0 | 2 | 0.00 | +| IBUFDS | 0 | 0 | 54 | 0.00 | +| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | +| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | +| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | +| ILOGIC | 0 | 0 | 54 | 0.00 | +| OLOGIC | 0 | 0 | 54 | 0.00 | ++-----------------------------+------+-------+-----------+-------+ + + +6. Clocking +----------- + ++------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++------------+------+-------+-----------+-------+ +| BUFGCTRL | 0 | 0 | 32 | 0.00 | +| BUFIO | 0 | 0 | 8 | 0.00 | +| MMCME2_ADV | 0 | 0 | 2 | 0.00 | +| PLLE2_ADV | 0 | 0 | 2 | 0.00 | +| BUFMRCE | 0 | 0 | 4 | 0.00 | +| BUFHCE | 0 | 0 | 48 | 0.00 | +| BUFR | 0 | 0 | 8 | 0.00 | ++------------+------+-------+-----------+-------+ + + +7. Specific Feature +------------------- + ++-------------+------+-------+-----------+-------+ +| Site Type | Used | Fixed | Available | Util% | ++-------------+------+-------+-----------+-------+ +| BSCANE2 | 0 | 0 | 4 | 0.00 | +| CAPTUREE2 | 0 | 0 | 1 | 0.00 | +| DNA_PORT | 0 | 0 | 1 | 0.00 | +| EFUSE_USR | 0 | 0 | 1 | 0.00 | +| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 | +| ICAPE2 | 0 | 0 | 2 | 0.00 | +| STARTUPE2 | 0 | 0 | 1 | 0.00 | +| XADC | 0 | 0 | 1 | 0.00 | ++-------------+------+-------+-----------+-------+ + + +8. Primitives +------------- + ++----------+------+---------------------+ +| Ref Name | Used | Functional Category | ++----------+------+---------------------+ + + +9. Black Boxes +-------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + +10. Instantiated Netlists +------------------------- + ++----------+------+ +| Ref Name | Used | ++----------+------+ + + diff --git a/esdi.runs/synth_1/gen_run.xml b/esdi.runs/synth_1/gen_run.xml new file mode 100644 index 0000000..9848585 --- /dev/null +++ b/esdi.runs/synth_1/gen_run.xml @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + diff --git a/esdi.runs/synth_1/htr.txt b/esdi.runs/synth_1/htr.txt new file mode 100644 index 0000000..22342a3 --- /dev/null +++ b/esdi.runs/synth_1/htr.txt @@ -0,0 +1,9 @@ +REM +REM Vivado(TM) +REM htr.txt: a Vivado-generated description of how-to-repeat the +REM the basic steps of a run. Note that runme.bat/sh needs +REM to be invoked for Vivado to track run status. +REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +REM + +vivado -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl diff --git a/esdi.runs/synth_1/project.wdf b/esdi.runs/synth_1/project.wdf new file mode 100644 index 0000000..a54295a --- /dev/null +++ b/esdi.runs/synth_1/project.wdf @@ -0,0 +1,31 @@ +version:1 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:41637469766548444c:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 +70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 +5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3766626462656662353231383438653961626661396637663131336536353232:506172656e742050412070726f6a656374204944:00 +eof:3165293120 diff --git a/esdi.runs/synth_1/rundef.js b/esdi.runs/synth_1/rundef.js new file mode 100644 index 0000000..f3457d8 --- /dev/null +++ b/esdi.runs/synth_1/rundef.js @@ -0,0 +1,36 @@ +// +// Vivado(TM) +// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6 +// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +// + +var WshShell = new ActiveXObject( "WScript.Shell" ); +var ProcEnv = WshShell.Environment( "Process" ); +var PathVal = ProcEnv("PATH"); +if ( PathVal.length == 0 ) { + PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;"; +} else { + PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;" + PathVal; +} + +ProcEnv("PATH") = PathVal; + +var RDScrFP = WScript.ScriptFullName; +var RDScrN = WScript.ScriptName; +var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); +var ISEJScriptLib = RDScrDir + "/ISEWrap.js"; +eval( EAInclude(ISEJScriptLib) ); + + +ISEStep( "vivado", + "-log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl" ); + + + +function EAInclude( EAInclFilename ) { + var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); + var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); + var EAIFContents = EAInclFile.ReadAll(); + EAInclFile.Close(); + return EAIFContents; +} diff --git a/esdi.runs/synth_1/runme.bat b/esdi.runs/synth_1/runme.bat new file mode 100644 index 0000000..bc78723 --- /dev/null +++ b/esdi.runs/synth_1/runme.bat @@ -0,0 +1,10 @@ +@echo off + +rem Vivado (TM) +rem runme.bat: a Vivado-generated Script +rem Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + + +set HD_SDIR=%~dp0 +cd /d "%HD_SDIR%" +cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %* diff --git a/esdi.runs/synth_1/runme.log b/esdi.runs/synth_1/runme.log new file mode 100644 index 0000000..677d299 --- /dev/null +++ b/esdi.runs/synth_1/runme.log @@ -0,0 +1,217 @@ + +*** Running vivado + with args -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl + + +****** Vivado v2019.1 (64-bit) + **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 + **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 + ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. + +source esdi_ctl_phy.tcl -notrace +Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1 +Starting synth_design +Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s' +INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s' +INFO: Launching helper process for spawning children vivado processes +INFO: Helper process launched with PID 18332 +--------------------------------------------------------------------------------- +Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551 +--------------------------------------------------------------------------------- +INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23] +INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23] +WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module +--------------------------------------------------------------------------------- +Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Loading Part and Timing Information +--------------------------------------------------------------------------------- +Loading part: xc7z007sclg225-1 +--------------------------------------------------------------------------------- +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- +INFO: [Device 21-403] Loading part xc7z007sclg225-1 +--------------------------------------------------------------------------------- +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start RTL Component Statistics +--------------------------------------------------------------------------------- +Detailed RTL Component Info : +--------------------------------------------------------------------------------- +Finished RTL Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +Hierarchical RTL Component report +--------------------------------------------------------------------------------- +Finished RTL Hierarchical Component Statistics +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Part Resource Summary +--------------------------------------------------------------------------------- +Part Resources: +DSPs: 66 (col length:40) +BRAMs: 100 (col length: RAMB18 40 RAMB36 20) +--------------------------------------------------------------------------------- +Finished Part Resource Summary +--------------------------------------------------------------------------------- +No constraint files found. +--------------------------------------------------------------------------------- +Start Cross Boundary and Area Optimization +--------------------------------------------------------------------------------- +Warning: Parallel synthesis criteria is not met +WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module +--------------------------------------------------------------------------------- +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +No constraint files found. +--------------------------------------------------------------------------------- +Start Timing Optimization +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Technology Mapping +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Flattening Before IO Insertion +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Final Netlist Cleanup +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report Check Netlist: ++------+------------------+-------+---------+-------+------------------+ +| |Item |Errors |Warnings |Status |Description | ++------+------------------+-------+---------+-------+------------------+ +|1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | ++------+------------------+-------+---------+-------+------------------+ +--------------------------------------------------------------------------------- +Start Renaming Generated Instances +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- + +Report RTL Partitions: ++-+--------------+------------+----------+ +| |RTL Partition |Replication |Instances | ++-+--------------+------------+----------+ ++-+--------------+------------+----------+ +--------------------------------------------------------------------------------- +Start Rebuilding User Hierarchy +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Ports +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Handling Custom Attributes +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Renaming Generated Nets +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start Writing Synthesis Report +--------------------------------------------------------------------------------- + +Report BlackBoxes: ++-+--------------+----------+ +| |BlackBox name |Instances | ++-+--------------+----------+ ++-+--------------+----------+ + +Report Cell Usage: ++------+-------------+------+ +| |Cell |Count | ++------+-------------+------+ +|1 |esdi_ctl_phy | 1| ++------+-------------+------+ + +Report Instance Areas: ++------+---------+-------+------+ +| |Instance |Module |Cells | ++------+---------+-------+------+ +|1 |top | | 0| ++------+---------+-------+------+ +--------------------------------------------------------------------------------- +Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +--------------------------------------------------------------------------------- +Synthesis finished with 0 errors, 0 critical warnings and 2 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211 +INFO: [Project 1-571] Translating synthesized netlist +INFO: [Project 1-570] Preparing netlist for logic optimization +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +INFO: [Common 17-83] Releasing license: Synthesis +9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered. +synth_design completed successfully +synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000 +WARNING: [Constraints 18-5210] No constraints selected for write. +Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened. +INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated. +INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb +INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019... diff --git a/esdi.runs/synth_1/runme.sh b/esdi.runs/synth_1/runme.sh new file mode 100644 index 0000000..5fd9210 --- /dev/null +++ b/esdi.runs/synth_1/runme.sh @@ -0,0 +1,43 @@ +#!/bin/sh + +# +# Vivado(TM) +# runme.sh: a Vivado-generated Runs Script for UNIX +# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. +# + +echo "This script was generated under a different operating system." +echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script" +exit + +if [ -z "$PATH" ]; then + PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin +else + PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin:$PATH +fi +export PATH + +if [ -z "$LD_LIBRARY_PATH" ]; then + LD_LIBRARY_PATH= +else + LD_LIBRARY_PATH=:$LD_LIBRARY_PATH +fi +export LD_LIBRARY_PATH + +HD_PWD='S:/vivado-projects/esdi/esdi/esdi.runs/synth_1' +cd "$HD_PWD" + +HD_LOG=runme.log +/bin/touch $HD_LOG + +ISEStep="./ISEWrap.sh" +EAStep() +{ + $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 + if [ $? -ne 0 ] + then + exit + fi +} + +EAStep vivado -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl diff --git a/esdi.runs/synth_1/vivado.jou b/esdi.runs/synth_1/vivado.jou new file mode 100644 index 0000000..7befed9 --- /dev/null +++ b/esdi.runs/synth_1/vivado.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# Vivado v2019.1 (64-bit) +# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019 +# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019 +# Start of session at: Tue Aug 13 10:38:50 2019 +# Process ID: 20424 +# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1 +# Command line: vivado.exe -log esdi_ctl_phy.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl +# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.vds +# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1\vivado.jou +#----------------------------------------------------------- +source esdi_ctl_phy.tcl -notrace diff --git a/esdi.runs/synth_1/vivado.pb b/esdi.runs/synth_1/vivado.pb new file mode 100644 index 0000000000000000000000000000000000000000..952d41b66a30ead2d80058c27efc9b7c13524746 GIT binary patch literal 21879 zcmeHP>u=n~5jXWXH(MbU&?HFIG+jFpY|FkAANTIVk!0CcZP}{i2cjYsXx>W4m`5JC zJXul?Zki$}3baU&qHWMGeSAvMq7U>-(SGiq)BmBfT#`o~c}EM8LfJmS@Ew=D<;?8N z?Ck994;`SXC9Bm^%|;#1QZzj=GgeaOUf9)l)rRG0hP;AGbl-HETMa_>9TVprtBnb5 z=v$g&Y_*&FINw%n2k&W>15vC{&DfFUQeKizH^{cyF`T;pWplEamn5Zmsy(qc@v(4f zdJNUkD;o~{S~qua_$`c%aj94f5yF10$Wr*%zZ1~g3ywotZMOr*!aKylDmHYDn3Ujc z%f{P8bvib|=Vs|S3|!7bTZ8Pv6K<3HB1NpuIiPtRWa5PQMj4P6Olr+_VrpdiYF7@9FXl#~FPt8rbGM9fUAQ}vV z&;0?xb$mx}5qzFrsAH|&!QaNBSZDtf{7p;@wM|JQ+*rV?q-ELr`26Z3{G?6Phj6#%|-IC@_ z^2oi(l%E+vVRu?c==xPOCM(lp@jF%FZDBK4&6lMTQl8kR}8B_y(q&(G2~ zXXyox{nF=U|79d37^*y=Ib&g!!onixjOUPMDQ>D1Y#TF2u#cI4;<_@Oo0(7)MSNl@ zu~A_^fEVTVa)XWKs&4AE3CjN@#!^f&mLeWtEM=uo3>%AFlnd38oMJ4GU4urxL2sk= z{89fUQ-Jmm7t^2ne99*RdK`#p$ug;9gY`T3o@(d~)zK|;uzPtvB$oY{-HU3?chHL4U9Xrhqqf|^OVNhxdAkwiO+nxAxnj{uJr=Hcu z|E*6uel4IM_q1dE&P{w9g5;Kdz+LYe%$Nkrhg6Buvo>ihN1a3-y@u9F+XAo0B*tt> zXEPP8;}rLBKibh{bn#;TVsr+MT!t<#9=hu;?ncOiOVWll4n4KX}KI?(3m)X_DXrajqn6rU}x5J%Mw2yvrKu@C^f zMv7u(&(Q7Y5LM8d!BiP#=xG|I?8W*{RICdq-_!i-IDW2YfXfysOH#w zra1AY@crnREur~{DMUC-@?IyN!R*cAdQ`+BdYzkv8;!3Mo;t!C9muoV`zKzWAMjW* z$R@mp?nM}(b#!H84T7R_8K2iI0~^HLahmm_cmXZ0FRa2HNfaZuFf=bpRa_L^Z%P@< z@Nhge20?X@QOJH+=ordeGA$@ z3g{QT1?`il%izUrH7O%o8?d;o)QW{F_^n|3La7uBvXr)ck-Y>*i(AO>1e4hDF3F#v z#qHIo6Dyz@?xDRLa5#;W;;phbf$S;xQ=c3ASU}w%h)59W$Z4^i>A-478M!0#Eb++e z$hywn%;IyM=d_5{G%ds0*~hDDyA7e($YwXNq#&i3;{x=zK5-jAR>?Wc(^cwuAD;AYs@$xkVfUHV*NUK~%HTPU$Oq z6U?51A&J_NNaNb+wxp;PYjNg+RwXa#VZmC)r$B-={NbG`JmXO*Wy2$Pb)BqzqpItzwQc@*7L9a z|J`NVwrr>@@ebzkl|794!K2z?BPP@jI3U=dfGI_q*)x?r1^?`G)4vtahrMl*VZwdh{dPQM zh?jEn&yiWG93X3O27^w(Hz#Hx{l;XC9MYSgK6Xj+a>2N}1hw7Hpd*Px zdh^NXEPrXFYs1IcN@g z-lGOPYEhf$YHya__Mu-M=}r@in7A8am*5*a&*7eZe8dlZFi4sPoU!*W3n@0@A*ckk zuM9z@_ug>bHC_i-%8;1`0W=-w)@xwXf8haXK<_UF^rHdvvSWn?aWW=&5#c+wYEq~S zVv!g1V7?Au%L#VxSjhzfT%~cPB+i}oprAGj_wOG-8T;*ZAA$}EKv^a#KgyfVCL50}X}MecJRo)?3S zo0=Jy%RLk|I5hyv54VbiLgJ5!3h>oj9Vp-gvH@1jgBD9-YWUr+q0=={Db&ifgpOZB zlVU*>6MA*Q+JI(|Nif4dMrZBCC^@@jVefauAT2oj zPw^uHC1-$nWKz}(X(U-c(=JJhXxClz$~yF+QYJDF$BqN@!Pr-oCxnE9jw|_U1ft}> z0=fo+#?J54OH8x;9enp<$@g7;tLwYqDQ~}@m>LV;fG1#tVFb$65Hugtx+LL4vz#y{ zhg02&V!jwb{rdr$0m6KBYGB&Y0PKQpcMM~n(-wveWXN!?rF-~=ae6k{8)Q&}0G05= z<1~%4=*2KS^`Yh<731_W3_@-!QaR!7P;-ErC9zVFY6+-sNd_@;5@1MuPT~eS3-+!B zkY*H9uvm>%E`X`yN9X{nko$x;Mg?q32-OHIN|(#5D`SauHx zF#*fcD~NC%|9DxJ0_%SRA&nImwJm^DOVEK0bU7W>(C(OkYUo0HN*vG71N1C3w068x zAil!pkchhi1WuM*D=RQ*n&&Lhabvs1GESZuff8% zw_KtMcH04H(FbXdwI3wMRlyAVzJOj@-s9O85VGoks0#%yR9P$sLY+amdoJo}oOc + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Vivado Synthesis Defaults + + + + + + + + + + + Default settings for Implementation. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- 2.41.0