| | 1 | update=8/14/2019 7:07:47 PM\r |
| | 2 | version=1\r |
| | 3 | last_client=kicad\r |
| | 4 | [general]\r |
| | 5 | version=1\r |
| | 6 | RootSch=\r |
| | 7 | BoardNm=\r |
| | 8 | [cvpcb]\r |
| | 9 | version=1\r |
| | 10 | NetIExt=net\r |
| | 11 | [eeschema]\r |
| | 12 | version=1\r |
| | 13 | LibDir=\r |
| | 14 | [eeschema/libraries]\r |
| | 15 | [pcbnew]\r |
| | 16 | version=1\r |
| | 17 | PageLayoutDescrFile=\r |
| | 18 | LastNetListRead=\r |
| | 19 | CopperLayerCount=2\r |
| | 20 | BoardThickness=1.6\r |
| | 21 | AllowMicroVias=0\r |
| | 22 | AllowBlindVias=0\r |
| | 23 | RequireCourtyardDefinitions=0\r |
| | 24 | ProhibitOverlappingCourtyards=1\r |
| | 25 | MinTrackWidth=0.3048\r |
| | 26 | MinViaDiameter=0.3048\r |
| | 27 | MinViaDrill=0.127\r |
| | 28 | MinMicroViaDiameter=0.3048\r |
| | 29 | MinMicroViaDrill=0.127\r |
| | 30 | MinHoleToHole=0.254\r |
| | 31 | TrackWidth1=0.3048\r |
| | 32 | ViaDiameter1=0.8\r |
| | 33 | ViaDrill1=0.4\r |
| | 34 | dPairWidth1=0.3048\r |
| | 35 | dPairGap1=0.25\r |
| | 36 | dPairViaGap1=0.25\r |
| | 37 | SilkLineWidth=0.12\r |
| | 38 | SilkTextSizeV=1\r |
| | 39 | SilkTextSizeH=1\r |
| | 40 | SilkTextSizeThickness=0.15\r |
| | 41 | SilkTextItalic=0\r |
| | 42 | SilkTextUpright=1\r |
| | 43 | CopperLineWidth=0.2\r |
| | 44 | CopperTextSizeV=1.5\r |
| | 45 | CopperTextSizeH=1.5\r |
| | 46 | CopperTextThickness=0.3\r |
| | 47 | CopperTextItalic=0\r |
| | 48 | CopperTextUpright=1\r |
| | 49 | EdgeCutLineWidth=0.05\r |
| | 50 | CourtyardLineWidth=0.05\r |
| | 51 | OthersLineWidth=0.15\r |
| | 52 | OthersTextSizeV=1\r |
| | 53 | OthersTextSizeH=1\r |
| | 54 | OthersTextSizeThickness=0.15\r |
| | 55 | OthersTextItalic=0\r |
| | 56 | OthersTextUpright=1\r |
| | 57 | SolderMaskClearance=0.051\r |
| | 58 | SolderMaskMinWidth=0.25\r |
| | 59 | SolderPasteClearance=0\r |
| | 60 | SolderPasteRatio=-0\r |
| | 61 | [pcbnew/Layer.F.Cu]\r |
| | 62 | Name=F.Cu\r |
| | 63 | Type=0\r |
| | 64 | Enabled=1\r |
| | 65 | [pcbnew/Layer.In1.Cu]\r |
| | 66 | Name=In1.Cu\r |
| | 67 | Type=0\r |
| | 68 | Enabled=0\r |
| | 69 | [pcbnew/Layer.In2.Cu]\r |
| | 70 | Name=In2.Cu\r |
| | 71 | Type=0\r |
| | 72 | Enabled=0\r |
| | 73 | [pcbnew/Layer.In3.Cu]\r |
| | 74 | Name=In3.Cu\r |
| | 75 | Type=0\r |
| | 76 | Enabled=0\r |
| | 77 | [pcbnew/Layer.In4.Cu]\r |
| | 78 | Name=In4.Cu\r |
| | 79 | Type=0\r |
| | 80 | Enabled=0\r |
| | 81 | [pcbnew/Layer.In5.Cu]\r |
| | 82 | Name=In5.Cu\r |
| | 83 | Type=0\r |
| | 84 | Enabled=0\r |
| | 85 | [pcbnew/Layer.In6.Cu]\r |
| | 86 | Name=In6.Cu\r |
| | 87 | Type=0\r |
| | 88 | Enabled=0\r |
| | 89 | [pcbnew/Layer.In7.Cu]\r |
| | 90 | Name=In7.Cu\r |
| | 91 | Type=0\r |
| | 92 | Enabled=0\r |
| | 93 | [pcbnew/Layer.In8.Cu]\r |
| | 94 | Name=In8.Cu\r |
| | 95 | Type=0\r |
| | 96 | Enabled=0\r |
| | 97 | [pcbnew/Layer.In9.Cu]\r |
| | 98 | Name=In9.Cu\r |
| | 99 | Type=0\r |
| | 100 | Enabled=0\r |
| | 101 | [pcbnew/Layer.In10.Cu]\r |
| | 102 | Name=In10.Cu\r |
| | 103 | Type=0\r |
| | 104 | Enabled=0\r |
| | 105 | [pcbnew/Layer.In11.Cu]\r |
| | 106 | Name=In11.Cu\r |
| | 107 | Type=0\r |
| | 108 | Enabled=0\r |
| | 109 | [pcbnew/Layer.In12.Cu]\r |
| | 110 | Name=In12.Cu\r |
| | 111 | Type=0\r |
| | 112 | Enabled=0\r |
| | 113 | [pcbnew/Layer.In13.Cu]\r |
| | 114 | Name=In13.Cu\r |
| | 115 | Type=0\r |
| | 116 | Enabled=0\r |
| | 117 | [pcbnew/Layer.In14.Cu]\r |
| | 118 | Name=In14.Cu\r |
| | 119 | Type=0\r |
| | 120 | Enabled=0\r |
| | 121 | [pcbnew/Layer.In15.Cu]\r |
| | 122 | Name=In15.Cu\r |
| | 123 | Type=0\r |
| | 124 | Enabled=0\r |
| | 125 | [pcbnew/Layer.In16.Cu]\r |
| | 126 | Name=In16.Cu\r |
| | 127 | Type=0\r |
| | 128 | Enabled=0\r |
| | 129 | [pcbnew/Layer.In17.Cu]\r |
| | 130 | Name=In17.Cu\r |
| | 131 | Type=0\r |
| | 132 | Enabled=0\r |
| | 133 | [pcbnew/Layer.In18.Cu]\r |
| | 134 | Name=In18.Cu\r |
| | 135 | Type=0\r |
| | 136 | Enabled=0\r |
| | 137 | [pcbnew/Layer.In19.Cu]\r |
| | 138 | Name=In19.Cu\r |
| | 139 | Type=0\r |
| | 140 | Enabled=0\r |
| | 141 | [pcbnew/Layer.In20.Cu]\r |
| | 142 | Name=In20.Cu\r |
| | 143 | Type=0\r |
| | 144 | Enabled=0\r |
| | 145 | [pcbnew/Layer.In21.Cu]\r |
| | 146 | Name=In21.Cu\r |
| | 147 | Type=0\r |
| | 148 | Enabled=0\r |
| | 149 | [pcbnew/Layer.In22.Cu]\r |
| | 150 | Name=In22.Cu\r |
| | 151 | Type=0\r |
| | 152 | Enabled=0\r |
| | 153 | [pcbnew/Layer.In23.Cu]\r |
| | 154 | Name=In23.Cu\r |
| | 155 | Type=0\r |
| | 156 | Enabled=0\r |
| | 157 | [pcbnew/Layer.In24.Cu]\r |
| | 158 | Name=In24.Cu\r |
| | 159 | Type=0\r |
| | 160 | Enabled=0\r |
| | 161 | [pcbnew/Layer.In25.Cu]\r |
| | 162 | Name=In25.Cu\r |
| | 163 | Type=0\r |
| | 164 | Enabled=0\r |
| | 165 | [pcbnew/Layer.In26.Cu]\r |
| | 166 | Name=In26.Cu\r |
| | 167 | Type=0\r |
| | 168 | Enabled=0\r |
| | 169 | [pcbnew/Layer.In27.Cu]\r |
| | 170 | Name=In27.Cu\r |
| | 171 | Type=0\r |
| | 172 | Enabled=0\r |
| | 173 | [pcbnew/Layer.In28.Cu]\r |
| | 174 | Name=In28.Cu\r |
| | 175 | Type=0\r |
| | 176 | Enabled=0\r |
| | 177 | [pcbnew/Layer.In29.Cu]\r |
| | 178 | Name=In29.Cu\r |
| | 179 | Type=0\r |
| | 180 | Enabled=0\r |
| | 181 | [pcbnew/Layer.In30.Cu]\r |
| | 182 | Name=In30.Cu\r |
| | 183 | Type=0\r |
| | 184 | Enabled=0\r |
| | 185 | [pcbnew/Layer.B.Cu]\r |
| | 186 | Name=B.Cu\r |
| | 187 | Type=0\r |
| | 188 | Enabled=1\r |
| | 189 | [pcbnew/Layer.B.Adhes]\r |
| | 190 | Enabled=1\r |
| | 191 | [pcbnew/Layer.F.Adhes]\r |
| | 192 | Enabled=1\r |
| | 193 | [pcbnew/Layer.B.Paste]\r |
| | 194 | Enabled=1\r |
| | 195 | [pcbnew/Layer.F.Paste]\r |
| | 196 | Enabled=1\r |
| | 197 | [pcbnew/Layer.B.SilkS]\r |
| | 198 | Enabled=1\r |
| | 199 | [pcbnew/Layer.F.SilkS]\r |
| | 200 | Enabled=1\r |
| | 201 | [pcbnew/Layer.B.Mask]\r |
| | 202 | Enabled=1\r |
| | 203 | [pcbnew/Layer.F.Mask]\r |
| | 204 | Enabled=1\r |
| | 205 | [pcbnew/Layer.Dwgs.User]\r |
| | 206 | Enabled=1\r |
| | 207 | [pcbnew/Layer.Cmts.User]\r |
| | 208 | Enabled=1\r |
| | 209 | [pcbnew/Layer.Eco1.User]\r |
| | 210 | Enabled=1\r |
| | 211 | [pcbnew/Layer.Eco2.User]\r |
| | 212 | Enabled=1\r |
| | 213 | [pcbnew/Layer.Edge.Cuts]\r |
| | 214 | Enabled=1\r |
| | 215 | [pcbnew/Layer.Margin]\r |
| | 216 | Enabled=1\r |
| | 217 | [pcbnew/Layer.B.CrtYd]\r |
| | 218 | Enabled=1\r |
| | 219 | [pcbnew/Layer.F.CrtYd]\r |
| | 220 | Enabled=1\r |
| | 221 | [pcbnew/Layer.B.Fab]\r |
| | 222 | Enabled=1\r |
| | 223 | [pcbnew/Layer.F.Fab]\r |
| | 224 | Enabled=1\r |
| | 225 | [pcbnew/Layer.Rescue]\r |
| | 226 | Enabled=0\r |
| | 227 | [pcbnew/Netclasses]\r |
| | 228 | [pcbnew/Netclasses/Default]\r |
| | 229 | Name=Default\r |
| | 230 | Clearance=0.2\r |
| | 231 | TrackWidth=0.3048\r |
| | 232 | ViaDiameter=0.8\r |
| | 233 | ViaDrill=0.4\r |
| | 234 | uViaDiameter=0.3048\r |
| | 235 | uViaDrill=0.127\r |
| | 236 | dPairWidth=0.3048\r |
| | 237 | dPairGap=0.25\r |
| | 238 | dPairViaGap=0.25\r |
| | 239 | [schematic_editor]\r |
| | 240 | version=1\r |
| | 241 | PageLayoutDescrFile=\r |
| | 242 | PlotDirectoryName=\r |
| | 243 | SubpartIdSeparator=0\r |
| | 244 | SubpartFirstId=65\r |
| | 245 | NetFmtName=\r |
| | 246 | SpiceAjustPassiveValues=0\r |
| | 247 | LabSize=197\r |
| | 248 | ERC_TestSimilarLabels=1\r |
projects / trav-board.git / blame_incremental