1 /* $OpenBSD: ti_iic.c,v 1.2 2014/03/18 14:23:52 rapha Exp $ */
2 /* $NetBSD: ti_iic.c,v 1.4 2013/04/25 13:04:27 rkujawa Exp $ */
5 * Copyright (c) 2013 Manuel Bouyer. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * Copyright (c) 2012 Jared D. McNeill <jmcneill@invisible.ca>
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
35 * 1. Redistributions of source code must retain the above copyright
36 * notice, this list of conditions and the following disclaimer.
37 * 2. The name of the author may not be used to endorse or promote products
38 * derived from this software without specific prior written permission.
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
41 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
42 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
43 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
46 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
53 #include <sys/cdefs.h>
54 #include <sys/param.h>
55 #include <sys/systm.h>
56 #include <sys/device.h>
57 #include <sys/kernel.h>
58 #include <sys/rwlock.h>
60 #include <machine/bus.h>
61 #include <machine/intr.h>
63 #include <dev/i2c/i2cvar.h>
65 #include <armv7/armv7/armv7var.h>
66 #include <armv7/omap/prcmvar.h>
67 #include <armv7/omap/sitara_cm.h>
68 #include <armv7/omap/sitara_cmreg.h>
69 #include <armv7/omap/ti_iicreg.h>
71 #ifndef AM335X_I2C_SLAVE_ADDR
72 #define AM335X_I2C_SLAVE_ADDR 0x01
76 #define DPRINTF(args) printf args
81 /* operation in progress */
91 struct i2c_controller sc_ic
;
92 struct rwlock sc_buslock
;
93 struct device
*sc_i2cdev
;
95 bus_space_tag_t sc_iot
;
96 bus_space_handle_t sc_ioh
;
109 #define I2C_READ_REG(sc, reg) \
110 bus_space_read_2((sc)->sc_iot, (sc)->sc_ioh, (reg))
111 #define I2C_READ_DATA(sc) \
112 bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA);
113 #define I2C_WRITE_REG(sc, reg, val) \
114 bus_space_write_2((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
115 #define I2C_WRITE_DATA(sc, val) \
116 bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, AM335X_I2C_DATA, (val))
118 #define DEVNAME(sc) ((sc)->sc_dev.dv_xname)
120 static void ti_iic_attach(struct device
*, struct device
*, void *);
121 static int ti_iic_intr(void *);
123 static int ti_iic_acquire_bus(void *, int);
124 static void ti_iic_release_bus(void *, int);
125 static int ti_iic_exec(void *, i2c_op_t
, i2c_addr_t
, const void *,
126 size_t, void *, size_t, int);
128 static int ti_iic_reset(struct ti_iic_softc
*);
129 static int ti_iic_op(struct ti_iic_softc
*, i2c_addr_t
, ti_i2cop_t
,
130 uint8_t *, size_t, int);
131 static void ti_iic_handle_intr(struct ti_iic_softc
*, uint32_t);
132 static void ti_iic_do_read(struct ti_iic_softc
*, uint32_t);
133 static void ti_iic_do_write(struct ti_iic_softc
*, uint32_t);
135 static int ti_iic_wait(struct ti_iic_softc
*, uint16_t, uint16_t, int);
136 static uint32_t ti_iic_stat(struct ti_iic_softc
*, uint32_t);
137 static int ti_iic_flush(struct ti_iic_softc
*);
139 struct cfattach tiiic_ca
= {
140 sizeof (struct ti_iic_softc
), NULL
, ti_iic_attach
143 struct cfdriver tiiic_cd
= {
144 NULL
, "tiiic", DV_DULL
148 ti_iic_attach(struct device
*parent
, struct device
*self
, void *args
)
150 struct ti_iic_softc
*sc
= (struct ti_iic_softc
*)self
;
151 struct armv7_attach_args
*aa
= args
;
152 struct i2cbus_attach_args iba
;
158 /* BBB specific pin names */
159 char *pins
[6] = {"I2C0_SDA", "I2C0_SCL",
160 "SPIO_D1", "SPI0_CS0",
161 "UART1_CTSn", "UART1_RTSn"};
163 sc
->sc_iot
= aa
->aa_iot
;
164 rw_init(&sc
->sc_buslock
, "tiiilk");
166 sc
->sc_rxthres
= sc
->sc_txthres
= 4;
168 if (bus_space_map(sc
->sc_iot
, aa
->aa_dev
->mem
[0].addr
,
169 aa
->aa_dev
->mem
[0].size
, 0, &sc
->sc_ioh
))
170 panic("%s: bus_space_map failed!");
172 sc
->sc_ih
= arm_intr_establish(aa
->aa_dev
->irq
[0], IPL_NET
,
173 ti_iic_intr
, sc
, DEVNAME(sc
));
175 prcm_enablemodule(PRCM_I2C0
+ aa
->aa_dev
->unit
);
177 if (board_id
== BOARD_ID_AM335X_BEAGLEBONE
) {
178 pin
= pins
[aa
->aa_dev
->unit
* 2];
179 snprintf(buf
, sizeof buf
, "I2C%d_SDA", aa
->aa_dev
->unit
);
180 if (sitara_cm_padconf_set(pin
, buf
,
181 (0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) {
182 printf(": can't switch %s pad\n", buf
);
185 if (sitara_cm_padconf_get(pin
, &mode
, &state
) == 0) {
186 printf(": %s state %d ", mode
, state
);
189 pin
= pins
[aa
->aa_dev
->unit
* 2 + 1];
190 snprintf(buf
, sizeof buf
, "I2C%d_SCL", aa
->aa_dev
->unit
);
191 if (sitara_cm_padconf_set(pin
, buf
,
192 (0x01 << 4) | (0x01 << 5) | (0x01 << 6)) != 0) {
193 printf(": can't switch %s pad\n", buf
);
196 if (sitara_cm_padconf_get(pin
, &mode
, &state
) == 0) {
197 printf(": %s state %d ", mode
, state
);
201 rev
= I2C_READ_REG(sc
, AM335X_I2C_REVNB_LO
);
202 printf(" rev %d.%d\n",
203 (int)I2C_REVNB_LO_MAJOR(rev
),
204 (int)I2C_REVNB_LO_MINOR(rev
));
209 sc
->sc_ic
.ic_cookie
= sc
;
210 sc
->sc_ic
.ic_acquire_bus
= ti_iic_acquire_bus
;
211 sc
->sc_ic
.ic_release_bus
= ti_iic_release_bus
;
212 sc
->sc_ic
.ic_exec
= ti_iic_exec
;
214 bzero(&iba
, sizeof iba
);
215 iba
.iba_name
= "iic";
216 iba
.iba_tag
= &sc
->sc_ic
;
217 (void) config_found(&sc
->sc_dev
, &iba
, iicbus_print
);
221 ti_iic_intr(void *arg
)
223 struct ti_iic_softc
*sc
= arg
;
226 DPRINTF(("ti_iic_intr\n"));
227 stat
= I2C_READ_REG(sc
, AM335X_I2C_IRQSTATUS
);
228 I2C_WRITE_REG(sc
, AM335X_I2C_IRQSTATUS
, stat
);
229 DPRINTF(("ti_iic_intr pre handle sc->sc_op eq %#x\n", sc
->sc_op
));
231 ti_iic_handle_intr(sc
, stat
);
233 if (sc
->sc_op
== TI_I2CERROR
|| sc
->sc_op
== TI_I2CDONE
) {
234 DPRINTF(("ti_iic_intr post handle sc->sc_op %#x\n", sc
->sc_op
));
238 DPRINTF(("ti_iic_intr status 0x%x\n", stat
));
244 ti_iic_acquire_bus(void *opaque
, int flags
)
246 struct ti_iic_softc
*sc
= opaque
;
248 if (flags
& I2C_F_POLL
)
251 return (rw_enter(&sc
->sc_buslock
, RW_WRITE
));
255 ti_iic_release_bus(void *opaque
, int flags
)
257 struct ti_iic_softc
*sc
= opaque
;
259 if (flags
& I2C_F_POLL
)
262 rw_exit(&sc
->sc_buslock
);
266 ti_iic_exec(void *opaque
, i2c_op_t op
, i2c_addr_t addr
,
267 const void *cmdbuf
, size_t cmdlen
, void *buf
, size_t len
, int flags
)
269 struct ti_iic_softc
*sc
= opaque
;
273 DPRINTF(("ti_iic_exec: op 0x%x cmdlen %zd len %zd flags 0x%x\n",
274 op
, cmdlen
, len
, flags
));
276 #define __UNCONST(a) ((void *)(unsigned long)(const void *)(a))
278 err
= ti_iic_op(sc
, addr
, TI_I2CWRITE
, __UNCONST(cmdbuf
),
279 cmdlen
, (I2C_OP_READ_P(op
) ? 0 : I2C_F_STOP
) | flags
);
283 if (I2C_OP_STOP_P(op
))
287 * I2C controller doesn't allow for zero-byte transfers.
292 if (I2C_OP_READ_P(op
))
293 err
= ti_iic_op(sc
, addr
, TI_I2CREAD
, buf
, len
, flags
);
295 err
= ti_iic_op(sc
, addr
, TI_I2CWRITE
, buf
, len
, flags
);
303 DPRINTF(("ti_iic_exec: done %d\n", err
));
308 ti_iic_reset(struct ti_iic_softc
*sc
)
310 uint32_t psc
, scll
, sclh
;
313 DPRINTF(("ti_iic_reset\n"));
316 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, 0);
318 I2C_WRITE_REG(sc
, AM335X_I2C_SYSC
, I2C_SYSC_SRST
);
320 /* enable so that we can check for reset complete */
321 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, I2C_CON_EN
);
323 for (i
= 0; i
< 1000; i
++) { /* 1s delay for reset */
324 if (I2C_READ_REG(sc
, AM335X_I2C_SYSS
) & I2C_SYSS_RDONE
)
328 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, 0);
332 printf("%s: couldn't reset module\n", DEVNAME(sc
));
336 /* XXX standard speed only */
342 I2C_WRITE_REG(sc
, AM335X_I2C_PSC
, psc
);
343 I2C_WRITE_REG(sc
, AM335X_I2C_SCLL
, scll
);
344 I2C_WRITE_REG(sc
, AM335X_I2C_SCLH
, sclh
);
346 /* Own I2C address */
347 I2C_WRITE_REG(sc
, AM335X_I2C_OA
, AM335X_I2C_SLAVE_ADDR
);
350 I2C_WRITE_REG(sc
, AM335X_I2C_BUF
,
351 I2C_BUF_RXTRSH(sc
->sc_rxthres
) | I2C_BUF_TXTRSH(sc
->sc_txthres
));
354 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, I2C_CON_EN
);
360 ti_iic_op(struct ti_iic_softc
*sc
, i2c_addr_t addr
, ti_i2cop_t op
,
361 uint8_t *buf
, size_t buflen
, int flags
)
363 uint16_t con
, stat
, mask
;
366 KASSERT(op
== TI_I2CREAD
|| op
== TI_I2CWRITE
);
367 DPRINTF(("ti_iic_op: addr %#x op %#x buf %p buflen %#x flags %#x\n",
368 addr
, op
, buf
, (unsigned int) buflen
, flags
));
370 mask
= I2C_IRQSTATUS_ARDY
| I2C_IRQSTATUS_NACK
| I2C_IRQSTATUS_AL
;
371 if (op
== TI_I2CREAD
)
372 mask
|= I2C_IRQSTATUS_RDR
| I2C_IRQSTATUS_RRDY
;
374 mask
|= I2C_IRQSTATUS_XDR
| I2C_IRQSTATUS_XRDY
;
376 err
= ti_iic_wait(sc
, I2C_IRQSTATUS_BB
, 0, flags
);
378 DPRINTF(("ti_iic_op: wait error %d\n", err
));
385 if (flags
& I2C_F_STOP
)
389 if (op
== TI_I2CWRITE
)
394 sc
->sc_buflen
= buflen
;
398 AM335X_I2C_CON
, I2C_CON_EN
| I2C_CON_MST
| I2C_CON_STP
);
399 DPRINTF(("ti_iic_op: op %d con 0x%x ", op
, con
));
400 I2C_WRITE_REG(sc
, AM335X_I2C_CNT
, buflen
);
401 I2C_WRITE_REG(sc
, AM335X_I2C_SA
, (addr
& I2C_SA_MASK
));
402 DPRINTF(("SA 0x%x len %d\n",
403 I2C_READ_REG(sc
, AM335X_I2C_SA
), I2C_READ_REG(sc
, AM335X_I2C_CNT
)));
405 if ((flags
& I2C_F_POLL
) == 0) {
406 /* clear any pending interrupt */
407 I2C_WRITE_REG(sc
, AM335X_I2C_IRQSTATUS
,
408 I2C_READ_REG(sc
, AM335X_I2C_IRQSTATUS
));
410 I2C_WRITE_REG(sc
, AM335X_I2C_IRQENABLE_SET
, mask
);
413 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, con
);
415 if ((flags
& I2C_F_POLL
) == 0) {
416 /* and wait for completion */
417 DPRINTF(("ti_iic_op waiting, op %#x\n", sc
->sc_op
));
418 while (sc
->sc_op
== op
) {
419 if (tsleep(&sc
->sc_dev
, PWAIT
, "tiiic", 500)
425 DPRINTF(("ti_iic_op waiting done, op %#x\n", sc
->sc_op
));
427 /* disable interrupts */
428 I2C_WRITE_REG(sc
, AM335X_I2C_IRQENABLE_CLR
, 0xffff);
430 /* poll for completion */
431 DPRINTF(("ti_iic_op polling, op %x\n", sc
->sc_op
));
432 while (sc
->sc_op
== op
) {
433 stat
= ti_iic_stat(sc
, mask
);
434 DPRINTF(("ti_iic_op stat 0x%x\n", stat
));
435 if (stat
== 0) /* timeout */
436 sc
->sc_op
= TI_I2CERROR
;
438 ti_iic_handle_intr(sc
, stat
);
439 I2C_WRITE_REG(sc
, AM335X_I2C_IRQSTATUS
, stat
);
441 DPRINTF(("ti_iic_op polling done, op now %x\n", sc
->sc_op
));
444 I2C_WRITE_REG(sc
, AM335X_I2C_CON
, 0);
445 while (I2C_READ_REG(sc
, AM335X_I2C_CON
) & I2C_CON_MST
) {
451 return (sc
->sc_op
== TI_I2CDONE
) ? 0 : EIO
;
455 ti_iic_handle_intr(struct ti_iic_softc
*sc
, uint32_t stat
)
458 DPRINTF(("ti_iic_handle_intr stat %#x\n", stat
));
460 if (stat
& (I2C_IRQSTATUS_NACK
|I2C_IRQSTATUS_AL
)) {
461 sc
->sc_op
= TI_I2CERROR
;
464 if (stat
& I2C_IRQSTATUS_ARDY
) {
465 sc
->sc_op
= TI_I2CDONE
;
468 if (sc
->sc_op
== TI_I2CREAD
)
469 ti_iic_do_read(sc
, stat
);
470 else if (sc
->sc_op
== TI_I2CWRITE
)
471 ti_iic_do_write(sc
, stat
);
476 ti_iic_do_read(struct ti_iic_softc
*sc
, uint32_t stat
)
480 DPRINTF(("ti_iic_do_read stat %#x\n", stat
));
481 if (stat
& I2C_IRQSTATUS_RDR
) {
482 len
= I2C_READ_REG(sc
, AM335X_I2C_BUFSTAT
);
483 len
= I2C_BUFSTAT_RXSTAT(len
);
484 DPRINTF(("ti_iic_do_read receive drain len %d left %d\n",
485 len
, I2C_READ_REG(sc
, AM335X_I2C_CNT
)));
486 } else if (stat
& I2C_IRQSTATUS_RRDY
) {
487 len
= sc
->sc_rxthres
+ 1;
488 DPRINTF(("ti_iic_do_read receive len %d left %d\n",
489 len
, I2C_READ_REG(sc
, AM335X_I2C_CNT
)));
492 sc
->sc_bufidx
< sc
->sc_buflen
&& len
> 0;
493 sc
->sc_bufidx
++, len
--) {
494 sc
->sc_buf
[sc
->sc_bufidx
] = I2C_READ_DATA(sc
);
495 DPRINTF(("ti_iic_do_read got b[%d]=0x%x\n", sc
->sc_bufidx
,
496 sc
->sc_buf
[sc
->sc_bufidx
]));
498 DPRINTF(("ti_iic_do_read done\n"));
502 ti_iic_do_write(struct ti_iic_softc
*sc
, uint32_t stat
)
506 DPRINTF(("ti_iic_do_write stat %#x\n", stat
));
508 if (stat
& I2C_IRQSTATUS_XDR
) {
509 len
= I2C_READ_REG(sc
, AM335X_I2C_BUFSTAT
);
510 len
= I2C_BUFSTAT_TXSTAT(len
);
511 DPRINTF(("ti_iic_do_write xmit drain len %d left %d\n",
512 len
, I2C_READ_REG(sc
, AM335X_I2C_CNT
)));
513 } else if (stat
& I2C_IRQSTATUS_XRDY
) {
514 len
= sc
->sc_txthres
+ 1;
515 DPRINTF(("ti_iic_do_write xmit len %d left %d\n",
516 len
, I2C_READ_REG(sc
, AM335X_I2C_CNT
)));
519 sc
->sc_bufidx
< sc
->sc_buflen
&& len
> 0;
520 sc
->sc_bufidx
++, len
--) {
521 DPRINTF(("ti_iic_do_write send b[%d]=0x%x\n",
522 sc
->sc_bufidx
, sc
->sc_buf
[sc
->sc_bufidx
]));
523 I2C_WRITE_DATA(sc
, sc
->sc_buf
[sc
->sc_bufidx
]);
525 DPRINTF(("ti_iic_do_write done\n"));
529 ti_iic_wait(struct ti_iic_softc
*sc
, uint16_t mask
, uint16_t val
, int flags
)
533 DPRINTF(("ti_iic_wait mask %#x val %#x flags %#x\n", mask
, val
, flags
));
535 while (((v
= I2C_READ_REG(sc
, AM335X_I2C_IRQSTATUS_RAW
)) & mask
) != val
) {
538 printf("%s: wait timeout, mask=%#x val=%#x stat=%#x\n",
539 DEVNAME(sc
), mask
, val
, v
);
542 if (flags
& I2C_F_POLL
)
545 tsleep(&sc
->sc_dev
, PWAIT
, "tiiic", 50);
547 DPRINTF(("ti_iic_wait done retry %#x\n", retry
));
553 ti_iic_stat(struct ti_iic_softc
*sc
, uint32_t mask
)
557 DPRINTF(("ti_iic_wait mask %#x\n", mask
));
558 while (--retry
> 0) {
559 v
= I2C_READ_REG(sc
, AM335X_I2C_IRQSTATUS_RAW
) & mask
;
564 DPRINTF(("ti_iic_wait done retry %#x\n", retry
));
569 ti_iic_flush(struct ti_iic_softc
*sc
)
571 DPRINTF(("ti_iic_flush\n"));
577 I2C_READ_REG(sc
, AM335X_I2C_IRQSTATUS_RAW
)) & I2C_IRQSTATUS_RRDY
) {
579 printf("%s: flush timeout, stat = %#x\n", DEVNAME(sc
), v
);
582 (void)I2C_READ_DATA(sc
);
587 I2C_WRITE_REG(sc
, AM335X_I2C_CNT
, 0);