[bbb-usb.git] / src / sys / arch / armv7 / omap / ammusb.h

/* $FreeBSD$ */
/*-
 * Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * This header file defines the registers of the Mentor Graphics USB OnTheGo
 * Inventra chip.
 */

#ifndef _MUSB2_OTG_H_
#define	_MUSB2_OTG_H_

#define	MUSB2_MAX_DEVICES USB_MAX_DEVICES

/* Common registers */

#define	MUSB2_REG_FADDR 0x0000		/* function address register */
#define	MUSB2_MASK_FADDR 0x7F

#define	MUSB2_REG_POWER 0x0001		/* power register */
#define	MUSB2_MASK_SUSPM_ENA 0x01
#define	MUSB2_MASK_SUSPMODE 0x02
#define	MUSB2_MASK_RESUME 0x04
#define	MUSB2_MASK_RESET 0x08
#define	MUSB2_MASK_HSMODE 0x10
#define	MUSB2_MASK_HSENAB 0x20
#define	MUSB2_MASK_SOFTC 0x40
#define	MUSB2_MASK_ISOUPD 0x80

/* Endpoint interrupt handling */

#define	MUSB2_REG_INTTX 0x0002		/* transmit interrupt register */
#define	MUSB2_REG_INTRX 0x0004		/* receive interrupt register */
#define	MUSB2_REG_INTTXE 0x0006		/* transmit interrupt enable register */
#define	MUSB2_REG_INTRXE 0x0008		/* receive interrupt enable register */
#define	MUSB2_MASK_EPINT(epn) (1 << (epn))	/* epn = [0..15] */

/* Common interrupt handling */

#define	MUSB2_REG_INTUSB 0x000A		/* USB interrupt register */
#define	MUSB2_MASK_ISUSP 0x01
#define	MUSB2_MASK_IRESUME 0x02
#define	MUSB2_MASK_IRESET 0x04
#define	MUSB2_MASK_IBABBLE 0x04
#define	MUSB2_MASK_ISOF 0x08
#define	MUSB2_MASK_ICONN 0x10
#define	MUSB2_MASK_IDISC 0x20
#define	MUSB2_MASK_ISESSRQ 0x40
#define	MUSB2_MASK_IVBUSERR 0x80

#define	MUSB2_REG_INTUSBE 0x000B	/* USB interrupt enable register */
#define	MUSB2_REG_FRAME 0x000C		/* USB frame register */
#define	MUSB2_MASK_FRAME 0x3FF		/* 0..1023 */

#define	MUSB2_REG_EPINDEX 0x000E	/* endpoint index register */
#define	MUSB2_MASK_EPINDEX 0x0F

#define	MUSB2_REG_TESTMODE 0x000F	/* test mode register */
#define	MUSB2_MASK_TSE0_NAK 0x01
#define	MUSB2_MASK_TJ 0x02
#define	MUSB2_MASK_TK 0x04
#define	MUSB2_MASK_TPACKET 0x08
#define	MUSB2_MASK_TFORCE_HS 0x10
#define	MUSB2_MASK_TFORCE_LS 0x20
#define	MUSB2_MASK_TFIFO_ACC 0x40
#define	MUSB2_MASK_TFORCE_HC 0x80

#define	MUSB2_REG_INDEXED_CSR 0x0010	/* EP control status register offset */

#define	MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_PKTSIZE 0x03FF	/* in bytes, should be even */
#define	MUSB2_MASK_PKTMULT 0xFC00	/* HS packet multiplier: 0..2 */

#define	MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_CSRL_TXPKTRDY 0x01
#define	MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02
#define	MUSB2_MASK_CSRL_TXUNDERRUN 0x04	/* Device Mode */
#define	MUSB2_MASK_CSRL_TXERROR 0x04	/* Host Mode */
#define	MUSB2_MASK_CSRL_TXFFLUSH 0x08
#define	MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */
#define	MUSB2_MASK_CSRL_TXSETUPPKT 0x10	/* Host Mode */
#define	MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */
#define	MUSB2_MASK_CSRL_TXSTALLED 0x20	/* Host Mode */
#define	MUSB2_MASK_CSRL_TXDT_CLR 0x40
#define	MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */
#define	MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */

/* Device Side Mode */
#define	MUSB2_MASK_CSR0L_RXPKTRDY 0x01
#define	MUSB2_MASK_CSR0L_TXPKTRDY 0x02
#define	MUSB2_MASK_CSR0L_SENTSTALL 0x04
#define	MUSB2_MASK_CSR0L_DATAEND 0x08
#define	MUSB2_MASK_CSR0L_SETUPEND 0x10
#define	MUSB2_MASK_CSR0L_SENDSTALL 0x20
#define	MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40
#define	MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80

/* Host Side Mode */
#define	MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02
#define	MUSB2_MASK_CSR0L_RXSTALL 0x04
#define	MUSB2_MASK_CSR0L_SETUPPKT 0x08
#define	MUSB2_MASK_CSR0L_ERROR 0x10
#define	MUSB2_MASK_CSR0L_REQPKT 0x20
#define	MUSB2_MASK_CSR0L_STATUSPKT 0x40
#define	MUSB2_MASK_CSR0L_NAKTIMO 0x80

#define	MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_CSRH_TXDT_VAL 0x01	/* Host Mode */
#define	MUSB2_MASK_CSRH_TXDT_WREN 0x02	/* Host Mode */
#define	MUSB2_MASK_CSRH_TXDMAREQMODE 0x04
#define	MUSB2_MASK_CSRH_TXDT_SWITCH 0x08
#define	MUSB2_MASK_CSRH_TXDMAREQENA 0x10
#define	MUSB2_MASK_CSRH_RXMODE 0x00
#define	MUSB2_MASK_CSRH_TXMODE 0x20
#define	MUSB2_MASK_CSRH_TXISO 0x40	/* Device Mode */
#define	MUSB2_MASK_CSRH_TXAUTOSET 0x80

#define	MUSB2_MASK_CSR0H_FFLUSH 0x01	/* Device Side flush FIFO */
#define	MUSB2_MASK_CSR0H_DT 0x02	/* Host Side data toggle */
#define	MUSB2_MASK_CSR0H_DT_WREN 0x04	/* Host Side */
#define	MUSB2_MASK_CSR0H_PING_DIS 0x08	/* Host Side */

#define	MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_CSRL_RXPKTRDY 0x01
#define	MUSB2_MASK_CSRL_RXFIFOFULL 0x02
#define	MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */
#define	MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */
#define	MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */
#define	MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */
#define	MUSB2_MASK_CSRL_RXFFLUSH 0x10
#define	MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */
#define	MUSB2_MASK_CSRL_RXREQPKT 0x20	/* Host Mode */
#define	MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */
#define	MUSB2_MASK_CSRL_RXSTALL 0x40	/* Host Mode */
#define	MUSB2_MASK_CSRL_RXDT_CLR 0x80

#define	MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_CSRH_RXINCOMP 0x01
#define	MUSB2_MASK_CSRH_RXDT_VAL 0x02	/* Host Mode */
#define	MUSB2_MASK_CSRH_RXDT_WREN 0x04	/* Host Mode */
#define	MUSB2_MASK_CSRH_RXDMAREQMODE 0x08
#define	MUSB2_MASK_CSRH_RXNYET 0x10
#define	MUSB2_MASK_CSRH_RXDMAREQENA 0x20
#define	MUSB2_MASK_CSRH_RXISO 0x40	/* Device Mode */
#define	MUSB2_MASK_CSRH_RXAUTOREQ 0x40	/* Host Mode */
#define	MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80

#define	MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_RXCOUNT 0xFFFF

#define	MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR)

/* Host Mode */
#define	MUSB2_MASK_TI_SPEED 0xC0
#define	MUSB2_MASK_TI_SPEED_LO 0xC0
#define	MUSB2_MASK_TI_SPEED_FS 0x80
#define	MUSB2_MASK_TI_SPEED_HS 0x40
#define	MUSB2_MASK_TI_PROTO_CTRL 0x00
#define	MUSB2_MASK_TI_PROTO_ISOC 0x10
#define	MUSB2_MASK_TI_PROTO_BULK 0x20
#define	MUSB2_MASK_TI_PROTO_INTR 0x30
#define	MUSB2_MASK_TI_EP_NUM 0x0F

#define	MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_NAKLIMIT 0xFF

#define	MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR)
#define	MUSB2_MASK_RX_FSIZE 0xF0	/* 3..13, 2**n bytes */
#define	MUSB2_MASK_TX_FSIZE 0x0F	/* 3..13, 2**n bytes */

#define	MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n)))

#define	MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR)	/* EPN=0 */
#define	MUSB2_MASK_CD_UTMI_DW 0x01
#define	MUSB2_MASK_CD_SOFTCONE 0x02
#define	MUSB2_MASK_CD_DYNFIFOSZ 0x04
#define	MUSB2_MASK_CD_HBTXE 0x08
#define	MUSB2_MASK_CD_HBRXE 0x10
#define	MUSB2_MASK_CD_BIGEND 0x20
#define	MUSB2_MASK_CD_MPTXE 0x40
#define	MUSB2_MASK_CD_MPRXE 0x80

/* Various registers */

#define	MUSB2_REG_DEVCTL 0x0060
#define	MUSB2_MASK_SESS 0x01
#define	MUSB2_MASK_HOSTREQ 0x02
#define	MUSB2_MASK_HOSTMD 0x04
#define	MUSB2_MASK_VBUS0 0x08
#define	MUSB2_MASK_VBUS1 0x10
#define	MUSB2_MASK_LSDEV 0x20
#define	MUSB2_MASK_FSDEV 0x40
#define	MUSB2_MASK_BDEV 0x80

#define	MUSB2_REG_MISC 0x0061
#define	MUSB2_MASK_RXEDMA 0x01
#define	MUSB2_MASK_TXEDMA 0x02

#define	MUSB2_REG_TXFIFOSZ 0x0062
#define	MUSB2_REG_RXFIFOSZ 0x0063
#define	MUSB2_MASK_FIFODB 0x10		/* set if double buffering, r/w */
#define	MUSB2_MASK_FIFOSZ 0x0F
#define	MUSB2_VAL_FIFOSZ_8 0
#define	MUSB2_VAL_FIFOSZ_16 1
#define	MUSB2_VAL_FIFOSZ_32 2
#define	MUSB2_VAL_FIFOSZ_64 3
#define	MUSB2_VAL_FIFOSZ_128 4
#define	MUSB2_VAL_FIFOSZ_256 5
#define	MUSB2_VAL_FIFOSZ_512 6
#define	MUSB2_VAL_FIFOSZ_1024 7
#define	MUSB2_VAL_FIFOSZ_2048 8
#define	MUSB2_VAL_FIFOSZ_4096 9

#define	MUSB2_REG_TXFIFOADD 0x0064
#define	MUSB2_REG_RXFIFOADD 0x0066
#define	MUSB2_MASK_FIFOADD 0xFFF	/* unit is 8-bytes */

#define	MUSB2_REG_VSTATUS 0x0068
#define	MUSB2_REG_VCONTROL 0x0068
#define	MUSB2_REG_HWVERS 0x006C
#define	MUSB2_REG_ULPI_BASE 0x0070

#define	MUSB2_REG_EPINFO 0x0078
#define	MUSB2_MASK_NRXEP 0xF0
#define	MUSB2_MASK_NTXEP 0x0F

#define	MUSB2_REG_RAMINFO 0x0079
#define	MUSB2_REG_LINKINFO 0x007A

#define	MUSB2_REG_VPLEN 0x007B
#define	MUSB2_MASK_VPLEN 0xFF

#define	MUSB2_REG_HS_EOF1 0x007C
#define	MUSB2_REG_FS_EOF1 0x007D
#define	MUSB2_REG_LS_EOF1 0x007E
#define	MUSB2_REG_SOFT_RST 0x007F
#define	MUSB2_MASK_SRST 0x01
#define	MUSB2_MASK_SRSTX 0x02

#define	MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n))
#define	MUSB2_REG_RXDBDIS 0x0340
#define	MUSB2_REG_TXDBDIS 0x0342
#define	MUSB2_MASK_DB(n) (1 << (n))	/* disable double buffer, n = [0..15] */

#define	MUSB2_REG_CHIRPTO 0x0344
#define	MUSB2_REG_HSRESUM 0x0346

/* Host Mode only registers */

#define	MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n)))
#define	MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n)))
#define	MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n)))
#define	MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n)))
#define	MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n)))
#define	MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n)))

#define	MUSB2_EP_MAX 16			/* maximum number of endpoints */

#define	MUSB2_DEVICE_MODE	0
#define	MUSB2_HOST_MODE		1

#define	MUSB2_READ_2(sc, reg) \
  bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

#define	MUSB2_WRITE_2(sc, reg, data)	\
  bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

#define	MUSB2_READ_1(sc, reg) \
  bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)

#define	MUSB2_WRITE_1(sc, reg, data)	\
  bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)

struct musbotg_td;
struct musbotg_softc;

typedef uint8_t (musbotg_cmd_t)(struct musbotg_td *td);

struct musbotg_dma {
	struct musbotg_softc *sc;
	uint32_t dma_chan;
	uint8_t	busy:1;
	uint8_t	complete:1;
	uint8_t	error:1;
};

struct musbotg_td {
	struct musbotg_td *obj_next;
	musbotg_cmd_t *func;
	struct usb_page_cache *pc;
	uint32_t offset;
	uint32_t remainder;
	uint16_t max_frame_size;	/* packet_size * mult */
	uint16_t reg_max_packet;
	uint8_t	ep_no;
	uint8_t	transfer_type;
	uint8_t	error:1;
	uint8_t	alt_next:1;
	uint8_t	short_pkt:1;
	uint8_t	support_multi_buffer:1;
	uint8_t	did_stall:1;
	uint8_t	dma_enabled:1;
	uint8_t	transaction_started:1;
	uint8_t dev_addr;
	uint8_t toggle;
	int8_t channel;
	uint8_t haddr;
	uint8_t hport;
};

struct musbotg_std_temp {
	musbotg_cmd_t *func;
	struct usb_page_cache *pc;
	struct musbotg_td *td;
	struct musbotg_td *td_next;
	uint32_t len;
	uint32_t offset;
	uint16_t max_frame_size;
	uint8_t	short_pkt;
	/*
         * short_pkt = 0: transfer should be short terminated
         * short_pkt = 1: transfer should not be short terminated
         */
	uint8_t	setup_alt_next;
	uint8_t did_stall;
	uint8_t dev_addr;
	int8_t channel;
	uint8_t haddr;
	uint8_t hport;
	uint8_t	transfer_type;
};

struct musbotg_config_desc {
	struct usb_config_descriptor confd;
	struct usb_interface_descriptor ifcd;
	struct usb_endpoint_descriptor endpd;
} __packed;

union musbotg_hub_temp {
	uWord	wValue;
	struct usb_port_status ps;
};

struct musbotg_flags {
	uint8_t	change_connect:1;
	uint8_t	change_suspend:1;
	uint8_t	change_reset:1;
	uint8_t	change_over_current:1;
	uint8_t	change_enabled:1;
	uint8_t	status_suspend:1;	/* set if suspended */
	uint8_t	status_vbus:1;		/* set if present */
	uint8_t	status_bus_reset:1;	/* set if reset complete */
	uint8_t	status_high_speed:1;	/* set if High Speed is selected */
	uint8_t	remote_wakeup:1;
	uint8_t	self_powered:1;
	uint8_t	clocks_off:1;
	uint8_t	port_powered:1;
	uint8_t	port_enabled:1;
	uint8_t	port_over_current:1;
	uint8_t	d_pulled_up:1;
};

struct musbotg_softc {
	struct usb_bus sc_bus;
	union musbotg_hub_temp sc_hub_temp;
	struct usb_hw_ep_profile sc_hw_ep_profile[MUSB2_EP_MAX];

	struct usb_device *sc_devices[MUSB2_MAX_DEVICES];
	struct resource *sc_io_res;
	struct resource *sc_irq_res;
	void   *sc_intr_hdl;
	bus_size_t sc_io_size;
	bus_space_tag_t sc_io_tag;
	bus_space_handle_t sc_io_hdl;

	void    (*sc_clocks_on) (void *arg);
	void    (*sc_clocks_off) (void *arg);
	void    (*sc_ep_int_set) (struct musbotg_softc *sc, int ep, int on);
	void   *sc_clocks_arg;

	uint32_t sc_bounce_buf[(1024 * 3) / 4];	/* bounce buffer */

	uint8_t	sc_ep_max;		/* maximum number of RX and TX
					 * endpoints supported */
	uint8_t	sc_rt_addr;		/* root HUB address */
	uint8_t	sc_dv_addr;		/* device address */
	uint8_t	sc_conf;		/* root HUB config */
	uint8_t	sc_ep0_busy;		/* set if ep0 is busy */
	uint8_t	sc_ep0_cmd;		/* pending commands */
	uint8_t	sc_conf_data;		/* copy of hardware register */

	uint8_t	sc_hub_idata[1];
	uint16_t sc_channel_mask;	/* 16 endpoints */

	struct musbotg_flags sc_flags;
	uint8_t	sc_id;
	uint8_t	sc_mode;
	void *sc_platform_data;
};

/* prototypes */

usb_error_t musbotg_init(struct musbotg_softc *sc);
void	musbotg_uninit(struct musbotg_softc *sc);
void	musbotg_interrupt(struct musbotg_softc *sc,
    uint16_t rxstat, uint16_t txstat, uint8_t stat);
void	musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on);
void	musbotg_connect_interrupt(struct musbotg_softc *sc);

#endif					/* _MUSB2_OTG_H_ */
Commit	Line	Data
8d587cd8	1	/* $FreeBSD$ */
	2	/*-
	3	* Copyright (c) 2008 Hans Petter Selasky. All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions
	7	* are met:
	8	* 1. Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer.
	10	* 2. Redistributions in binary form must reproduce the above copyright
	11	* notice, this list of conditions and the following disclaimer in the
	12	* documentation and/or other materials provided with the distribution.
	13	*
	14	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
	15	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
	16	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
	17	* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
	18	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
	19	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
	20	* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
	21	* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
	22	* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
	23	* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
	24	* SUCH DAMAGE.
	25	*/
	26
	27	/*
	28	* This header file defines the registers of the Mentor Graphics USB OnTheGo
	29	* Inventra chip.
	30	*/
	31
	32	#ifndef _MUSB2_OTG_H_
	33	#define _MUSB2_OTG_H_
	34
	35	#define MUSB2_MAX_DEVICES USB_MAX_DEVICES
	36
	37	/* Common registers */
	38
	39	#define MUSB2_REG_FADDR 0x0000 /* function address register */
	40	#define MUSB2_MASK_FADDR 0x7F
	41
	42	#define MUSB2_REG_POWER 0x0001 /* power register */
	43	#define MUSB2_MASK_SUSPM_ENA 0x01
	44	#define MUSB2_MASK_SUSPMODE 0x02
	45	#define MUSB2_MASK_RESUME 0x04
	46	#define MUSB2_MASK_RESET 0x08
	47	#define MUSB2_MASK_HSMODE 0x10
	48	#define MUSB2_MASK_HSENAB 0x20
	49	#define MUSB2_MASK_SOFTC 0x40
	50	#define MUSB2_MASK_ISOUPD 0x80
	51
	52	/* Endpoint interrupt handling */
	53
	54	#define MUSB2_REG_INTTX 0x0002 /* transmit interrupt register */
	55	#define MUSB2_REG_INTRX 0x0004 /* receive interrupt register */
	56	#define MUSB2_REG_INTTXE 0x0006 /* transmit interrupt enable register */
	57	#define MUSB2_REG_INTRXE 0x0008 /* receive interrupt enable register */
	58	#define MUSB2_MASK_EPINT(epn) (1 << (epn)) /* epn = [0..15] */
	59
	60	/* Common interrupt handling */
	61
	62	#define MUSB2_REG_INTUSB 0x000A /* USB interrupt register */
	63	#define MUSB2_MASK_ISUSP 0x01
	64	#define MUSB2_MASK_IRESUME 0x02
65	#define MUSB2_MASK_IRESET 0x04
66	#define MUSB2_MASK_IBABBLE 0x04
67	#define MUSB2_MASK_ISOF 0x08
68	#define MUSB2_MASK_ICONN 0x10
69	#define MUSB2_MASK_IDISC 0x20
70	#define MUSB2_MASK_ISESSRQ 0x40
71	#define MUSB2_MASK_IVBUSERR 0x80
72
73	#define MUSB2_REG_INTUSBE 0x000B /* USB interrupt enable register */
74	#define MUSB2_REG_FRAME 0x000C /* USB frame register */
75	#define MUSB2_MASK_FRAME 0x3FF /* 0..1023 */
76
77	#define MUSB2_REG_EPINDEX 0x000E /* endpoint index register */
78	#define MUSB2_MASK_EPINDEX 0x0F
79
80	#define MUSB2_REG_TESTMODE 0x000F /* test mode register */
81	#define MUSB2_MASK_TSE0_NAK 0x01
82	#define MUSB2_MASK_TJ 0x02
83	#define MUSB2_MASK_TK 0x04
84	#define MUSB2_MASK_TPACKET 0x08
85	#define MUSB2_MASK_TFORCE_HS 0x10
86	#define MUSB2_MASK_TFORCE_LS 0x20
87	#define MUSB2_MASK_TFIFO_ACC 0x40
88	#define MUSB2_MASK_TFORCE_HC 0x80
89
90	#define MUSB2_REG_INDEXED_CSR 0x0010 /* EP control status register offset */
91
92	#define MUSB2_REG_TXMAXP (0x0000 + MUSB2_REG_INDEXED_CSR)
93	#define MUSB2_REG_RXMAXP (0x0004 + MUSB2_REG_INDEXED_CSR)
94	#define MUSB2_MASK_PKTSIZE 0x03FF /* in bytes, should be even */
95	#define MUSB2_MASK_PKTMULT 0xFC00 /* HS packet multiplier: 0..2 */
96
97	#define MUSB2_REG_TXCSRL (0x0002 + MUSB2_REG_INDEXED_CSR)
98	#define MUSB2_MASK_CSRL_TXPKTRDY 0x01
99	#define MUSB2_MASK_CSRL_TXFIFONEMPTY 0x02
100	#define MUSB2_MASK_CSRL_TXUNDERRUN 0x04 /* Device Mode */
101	#define MUSB2_MASK_CSRL_TXERROR 0x04 /* Host Mode */
102	#define MUSB2_MASK_CSRL_TXFFLUSH 0x08
103	#define MUSB2_MASK_CSRL_TXSENDSTALL 0x10/* Device Mode */
104	#define MUSB2_MASK_CSRL_TXSETUPPKT 0x10 /* Host Mode */
105	#define MUSB2_MASK_CSRL_TXSENTSTALL 0x20/* Device Mode */
106	#define MUSB2_MASK_CSRL_TXSTALLED 0x20 /* Host Mode */
107	#define MUSB2_MASK_CSRL_TXDT_CLR 0x40
108	#define MUSB2_MASK_CSRL_TXINCOMP 0x80 /* Device mode */
109	#define MUSB2_MASK_CSRL_TXNAKTO 0x80 /* Host mode */
110
111	/* Device Side Mode */
112	#define MUSB2_MASK_CSR0L_RXPKTRDY 0x01
113	#define MUSB2_MASK_CSR0L_TXPKTRDY 0x02
114	#define MUSB2_MASK_CSR0L_SENTSTALL 0x04
115	#define MUSB2_MASK_CSR0L_DATAEND 0x08
116	#define MUSB2_MASK_CSR0L_SETUPEND 0x10
117	#define MUSB2_MASK_CSR0L_SENDSTALL 0x20
118	#define MUSB2_MASK_CSR0L_RXPKTRDY_CLR 0x40
119	#define MUSB2_MASK_CSR0L_SETUPEND_CLR 0x80
120
121	/* Host Side Mode */
122	#define MUSB2_MASK_CSR0L_TXFIFONEMPTY 0x02
123	#define MUSB2_MASK_CSR0L_RXSTALL 0x04
124	#define MUSB2_MASK_CSR0L_SETUPPKT 0x08
125	#define MUSB2_MASK_CSR0L_ERROR 0x10
126	#define MUSB2_MASK_CSR0L_REQPKT 0x20
127	#define MUSB2_MASK_CSR0L_STATUSPKT 0x40
128	#define MUSB2_MASK_CSR0L_NAKTIMO 0x80
129
130	#define MUSB2_REG_TXCSRH (0x0003 + MUSB2_REG_INDEXED_CSR)
131	#define MUSB2_MASK_CSRH_TXDT_VAL 0x01 /* Host Mode */
132	#define MUSB2_MASK_CSRH_TXDT_WREN 0x02 /* Host Mode */
133	#define MUSB2_MASK_CSRH_TXDMAREQMODE 0x04
134	#define MUSB2_MASK_CSRH_TXDT_SWITCH 0x08
135	#define MUSB2_MASK_CSRH_TXDMAREQENA 0x10
136	#define MUSB2_MASK_CSRH_RXMODE 0x00
137	#define MUSB2_MASK_CSRH_TXMODE 0x20
138	#define MUSB2_MASK_CSRH_TXISO 0x40 /* Device Mode */
139	#define MUSB2_MASK_CSRH_TXAUTOSET 0x80
140
141	#define MUSB2_MASK_CSR0H_FFLUSH 0x01 /* Device Side flush FIFO */
142	#define MUSB2_MASK_CSR0H_DT 0x02 /* Host Side data toggle */
143	#define MUSB2_MASK_CSR0H_DT_WREN 0x04 /* Host Side */
144	#define MUSB2_MASK_CSR0H_PING_DIS 0x08 /* Host Side */
145
146	#define MUSB2_REG_RXCSRL (0x0006 + MUSB2_REG_INDEXED_CSR)
147	#define MUSB2_MASK_CSRL_RXPKTRDY 0x01
148	#define MUSB2_MASK_CSRL_RXFIFOFULL 0x02
149	#define MUSB2_MASK_CSRL_RXOVERRUN 0x04 /* Device Mode */
150	#define MUSB2_MASK_CSRL_RXERROR 0x04 /* Host Mode */
151	#define MUSB2_MASK_CSRL_RXDATAERR 0x08 /* Device Mode */
152	#define MUSB2_MASK_CSRL_RXNAKTO 0x08 /* Host Mode */
153	#define MUSB2_MASK_CSRL_RXFFLUSH 0x10
154	#define MUSB2_MASK_CSRL_RXSENDSTALL 0x20/* Device Mode */
155	#define MUSB2_MASK_CSRL_RXREQPKT 0x20 /* Host Mode */
156	#define MUSB2_MASK_CSRL_RXSENTSTALL 0x40/* Device Mode */
157	#define MUSB2_MASK_CSRL_RXSTALL 0x40 /* Host Mode */
158	#define MUSB2_MASK_CSRL_RXDT_CLR 0x80
159
160	#define MUSB2_REG_RXCSRH (0x0007 + MUSB2_REG_INDEXED_CSR)
161	#define MUSB2_MASK_CSRH_RXINCOMP 0x01
162	#define MUSB2_MASK_CSRH_RXDT_VAL 0x02 /* Host Mode */
163	#define MUSB2_MASK_CSRH_RXDT_WREN 0x04 /* Host Mode */
164	#define MUSB2_MASK_CSRH_RXDMAREQMODE 0x08
165	#define MUSB2_MASK_CSRH_RXNYET 0x10
166	#define MUSB2_MASK_CSRH_RXDMAREQENA 0x20
167	#define MUSB2_MASK_CSRH_RXISO 0x40 /* Device Mode */
168	#define MUSB2_MASK_CSRH_RXAUTOREQ 0x40 /* Host Mode */
169	#define MUSB2_MASK_CSRH_RXAUTOCLEAR 0x80
170
171	#define MUSB2_REG_RXCOUNT (0x0008 + MUSB2_REG_INDEXED_CSR)
172	#define MUSB2_MASK_RXCOUNT 0xFFFF
173
174	#define MUSB2_REG_TXTI (0x000A + MUSB2_REG_INDEXED_CSR)
175	#define MUSB2_REG_RXTI (0x000C + MUSB2_REG_INDEXED_CSR)
176
177	/* Host Mode */
178	#define MUSB2_MASK_TI_SPEED 0xC0
179	#define MUSB2_MASK_TI_SPEED_LO 0xC0
180	#define MUSB2_MASK_TI_SPEED_FS 0x80
181	#define MUSB2_MASK_TI_SPEED_HS 0x40
182	#define MUSB2_MASK_TI_PROTO_CTRL 0x00
183	#define MUSB2_MASK_TI_PROTO_ISOC 0x10
184	#define MUSB2_MASK_TI_PROTO_BULK 0x20
185	#define MUSB2_MASK_TI_PROTO_INTR 0x30
186	#define MUSB2_MASK_TI_EP_NUM 0x0F
187
188	#define MUSB2_REG_TXNAKLIMIT (0x000B /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
189	#define MUSB2_REG_RXNAKLIMIT (0x000D /* EPN=0 */ + MUSB2_REG_INDEXED_CSR)
190	#define MUSB2_MASK_NAKLIMIT 0xFF
191
192	#define MUSB2_REG_FSIZE (0x000F + MUSB2_REG_INDEXED_CSR)
193	#define MUSB2_MASK_RX_FSIZE 0xF0 /* 3..13, 2*n bytes /
194	#define MUSB2_MASK_TX_FSIZE 0x0F /* 3..13, 2*n bytes /
195
196	#define MUSB2_REG_EPFIFO(n) (0x0020 + (4*(n)))
197
198	#define MUSB2_REG_CONFDATA (0x000F + MUSB2_REG_INDEXED_CSR) /* EPN=0 */
199	#define MUSB2_MASK_CD_UTMI_DW 0x01
200	#define MUSB2_MASK_CD_SOFTCONE 0x02
201	#define MUSB2_MASK_CD_DYNFIFOSZ 0x04
202	#define MUSB2_MASK_CD_HBTXE 0x08
203	#define MUSB2_MASK_CD_HBRXE 0x10
204	#define MUSB2_MASK_CD_BIGEND 0x20
205	#define MUSB2_MASK_CD_MPTXE 0x40
206	#define MUSB2_MASK_CD_MPRXE 0x80
207
208	/* Various registers */
209
210	#define MUSB2_REG_DEVCTL 0x0060
211	#define MUSB2_MASK_SESS 0x01
212	#define MUSB2_MASK_HOSTREQ 0x02
213	#define MUSB2_MASK_HOSTMD 0x04
214	#define MUSB2_MASK_VBUS0 0x08
215	#define MUSB2_MASK_VBUS1 0x10
216	#define MUSB2_MASK_LSDEV 0x20
217	#define MUSB2_MASK_FSDEV 0x40
218	#define MUSB2_MASK_BDEV 0x80
219
220	#define MUSB2_REG_MISC 0x0061
221	#define MUSB2_MASK_RXEDMA 0x01
222	#define MUSB2_MASK_TXEDMA 0x02
223
224	#define MUSB2_REG_TXFIFOSZ 0x0062
225	#define MUSB2_REG_RXFIFOSZ 0x0063
226	#define MUSB2_MASK_FIFODB 0x10 /* set if double buffering, r/w */
227	#define MUSB2_MASK_FIFOSZ 0x0F
228	#define MUSB2_VAL_FIFOSZ_8 0
229	#define MUSB2_VAL_FIFOSZ_16 1
230	#define MUSB2_VAL_FIFOSZ_32 2
231	#define MUSB2_VAL_FIFOSZ_64 3
232	#define MUSB2_VAL_FIFOSZ_128 4
233	#define MUSB2_VAL_FIFOSZ_256 5
234	#define MUSB2_VAL_FIFOSZ_512 6
235	#define MUSB2_VAL_FIFOSZ_1024 7
236	#define MUSB2_VAL_FIFOSZ_2048 8
237	#define MUSB2_VAL_FIFOSZ_4096 9
238
239	#define MUSB2_REG_TXFIFOADD 0x0064
240	#define MUSB2_REG_RXFIFOADD 0x0066
241	#define MUSB2_MASK_FIFOADD 0xFFF /* unit is 8-bytes */
242
243	#define MUSB2_REG_VSTATUS 0x0068
244	#define MUSB2_REG_VCONTROL 0x0068
245	#define MUSB2_REG_HWVERS 0x006C
246	#define MUSB2_REG_ULPI_BASE 0x0070
247
248	#define MUSB2_REG_EPINFO 0x0078
249	#define MUSB2_MASK_NRXEP 0xF0
250	#define MUSB2_MASK_NTXEP 0x0F
251
252	#define MUSB2_REG_RAMINFO 0x0079
253	#define MUSB2_REG_LINKINFO 0x007A
254
255	#define MUSB2_REG_VPLEN 0x007B
256	#define MUSB2_MASK_VPLEN 0xFF
257
258	#define MUSB2_REG_HS_EOF1 0x007C
259	#define MUSB2_REG_FS_EOF1 0x007D
260	#define MUSB2_REG_LS_EOF1 0x007E
261	#define MUSB2_REG_SOFT_RST 0x007F
262	#define MUSB2_MASK_SRST 0x01
263	#define MUSB2_MASK_SRSTX 0x02
264
265	#define MUSB2_REG_RQPKTCOUNT(n) (0x0300 + (4*(n))
266	#define MUSB2_REG_RXDBDIS 0x0340
267	#define MUSB2_REG_TXDBDIS 0x0342
268	#define MUSB2_MASK_DB(n) (1 << (n)) /* disable double buffer, n = [0..15] */
269
270	#define MUSB2_REG_CHIRPTO 0x0344
271	#define MUSB2_REG_HSRESUM 0x0346
272
273	/* Host Mode only registers */
274
275	#define MUSB2_REG_TXFADDR(n) (0x0080 + (8*(n)))
276	#define MUSB2_REG_TXHADDR(n) (0x0082 + (8*(n)))
277	#define MUSB2_REG_TXHUBPORT(n) (0x0083 + (8*(n)))
278	#define MUSB2_REG_RXFADDR(n) (0x0084 + (8*(n)))
279	#define MUSB2_REG_RXHADDR(n) (0x0086 + (8*(n)))
280	#define MUSB2_REG_RXHUBPORT(n) (0x0087 + (8*(n)))
281
282	#define MUSB2_EP_MAX 16 /* maximum number of endpoints */
283
284	#define MUSB2_DEVICE_MODE 0
285	#define MUSB2_HOST_MODE 1
286
287	#define MUSB2_READ_2(sc, reg) \
288	bus_space_read_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
289
290	#define MUSB2_WRITE_2(sc, reg, data) \
291	bus_space_write_2((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
292
293	#define MUSB2_READ_1(sc, reg) \
294	bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg)
295
296	#define MUSB2_WRITE_1(sc, reg, data) \
297	bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, reg, data)
298
299	struct musbotg_td;
300	struct musbotg_softc;
301
302	typedef uint8_t (musbotg_cmd_t)(struct musbotg_td *td);
303
304	struct musbotg_dma {
305	struct musbotg_softc *sc;
306	uint32_t dma_chan;
307	uint8_t busy:1;
308	uint8_t complete:1;
309	uint8_t error:1;
310	};
311
312	struct musbotg_td {
313	struct musbotg_td *obj_next;
314	musbotg_cmd_t *func;
315	struct usb_page_cache *pc;
316	uint32_t offset;
317	uint32_t remainder;
318	uint16_t max_frame_size; /* packet_size * mult */
319	uint16_t reg_max_packet;
320	uint8_t ep_no;
321	uint8_t transfer_type;
322	uint8_t error:1;
323	uint8_t alt_next:1;
324	uint8_t short_pkt:1;
325	uint8_t support_multi_buffer:1;
326	uint8_t did_stall:1;
327	uint8_t dma_enabled:1;
328	uint8_t transaction_started:1;
329	uint8_t dev_addr;
330	uint8_t toggle;
331	int8_t channel;
332	uint8_t haddr;
333	uint8_t hport;
334	};
335
336	struct musbotg_std_temp {
337	musbotg_cmd_t *func;
338	struct usb_page_cache *pc;
339	struct musbotg_td *td;
340	struct musbotg_td *td_next;
341	uint32_t len;
342	uint32_t offset;
343	uint16_t max_frame_size;
344	uint8_t short_pkt;
345	/*
346	* short_pkt = 0: transfer should be short terminated
347	* short_pkt = 1: transfer should not be short terminated
348	*/
349	uint8_t setup_alt_next;
350	uint8_t did_stall;
351	uint8_t dev_addr;
352	int8_t channel;
353	uint8_t haddr;
354	uint8_t hport;
355	uint8_t transfer_type;
356	};
357
358	struct musbotg_config_desc {
359	struct usb_config_descriptor confd;
360	struct usb_interface_descriptor ifcd;
361	struct usb_endpoint_descriptor endpd;
362	} __packed;
363
364	union musbotg_hub_temp {
365	uWord wValue;
366	struct usb_port_status ps;
367	};
368
369	struct musbotg_flags {
370	uint8_t change_connect:1;
371	uint8_t change_suspend:1;
372	uint8_t change_reset:1;
373	uint8_t change_over_current:1;
374	uint8_t change_enabled:1;
375	uint8_t status_suspend:1; /* set if suspended */
376	uint8_t status_vbus:1; /* set if present */
377	uint8_t status_bus_reset:1; /* set if reset complete */
378	uint8_t status_high_speed:1; /* set if High Speed is selected */
379	uint8_t remote_wakeup:1;
380	uint8_t self_powered:1;
381	uint8_t clocks_off:1;
382	uint8_t port_powered:1;
383	uint8_t port_enabled:1;
384	uint8_t port_over_current:1;
385	uint8_t d_pulled_up:1;
386	};
387
388	struct musbotg_softc {
389	struct usb_bus sc_bus;
390	union musbotg_hub_temp sc_hub_temp;
391	struct usb_hw_ep_profile sc_hw_ep_profile[MUSB2_EP_MAX];
392
393	struct usb_device *sc_devices[MUSB2_MAX_DEVICES];
394	struct resource *sc_io_res;
395	struct resource *sc_irq_res;
396	void *sc_intr_hdl;
397	bus_size_t sc_io_size;
398	bus_space_tag_t sc_io_tag;
399	bus_space_handle_t sc_io_hdl;
400
401	void (sc_clocks_on) (void arg);
402	void (sc_clocks_off) (void arg);
403	void (sc_ep_int_set) (struct musbotg_softc sc, int ep, int on);
404	void *sc_clocks_arg;
405
406	uint32_t sc_bounce_buf[(1024 * 3) / 4]; /* bounce buffer */
407
408	uint8_t sc_ep_max; /* maximum number of RX and TX
409	* endpoints supported */
410	uint8_t sc_rt_addr; /* root HUB address */
411	uint8_t sc_dv_addr; /* device address */
412	uint8_t sc_conf; /* root HUB config */
413	uint8_t sc_ep0_busy; /* set if ep0 is busy */
414	uint8_t sc_ep0_cmd; /* pending commands */
415	uint8_t sc_conf_data; /* copy of hardware register */
416
417	uint8_t sc_hub_idata[1];
418	uint16_t sc_channel_mask; /* 16 endpoints */
419
420	struct musbotg_flags sc_flags;
421	uint8_t sc_id;
422	uint8_t sc_mode;
423	void *sc_platform_data;
424	};
425
426	/* prototypes */
427
428	usb_error_t musbotg_init(struct musbotg_softc *sc);
429	void musbotg_uninit(struct musbotg_softc *sc);
430	void musbotg_interrupt(struct musbotg_softc *sc,
431	uint16_t rxstat, uint16_t txstat, uint8_t stat);
432	void musbotg_vbus_interrupt(struct musbotg_softc *sc, uint8_t is_on);
433	void musbotg_connect_interrupt(struct musbotg_softc *sc);
434
435	#endif /* _MUSB2_OTG_H_ */
436