| 1 | \r |
| 2 | *** Running vivado\r |
| 3 | with args -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace\r |
| 4 | \r |
| 5 | \r |
| 6 | ****** Vivado v2019.1 (64-bit)\r |
| 7 | **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019\r |
| 8 | **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019\r |
| 9 | ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r |
| 10 | \r |
| 11 | source esdi_ctl_phy.tcl -notrace\r |
| 12 | Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1\r |
| 13 | Design is defaulting to srcset: sources_1\r |
| 14 | Design is defaulting to constrset: constrs_1\r |
| 15 | INFO: [Device 21-403] Loading part xc7z007sclg225-1\r |
| 16 | INFO: [Project 1-479] Netlist was created with Vivado 2019.1\r |
| 17 | INFO: [Project 1-570] Preparing netlist for logic optimization\r |
| 18 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000\r |
| 19 | INFO: [Project 1-111] Unisim Transformation Summary:\r |
| 20 | No Unisim elements were transformed.\r |
| 21 | \r |
| 22 | 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r |
| 23 | link_design completed successfully\r |
| 24 | link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582\r |
| 25 | Command: opt_design\r |
| 26 | Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r |
| 27 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r |
| 28 | Running DRC as a precondition to command opt_design\r |
| 29 | \r |
| 30 | Starting DRC Task\r |
| 31 | INFO: [DRC 23-27] Running DRC with 2 threads\r |
| 32 | INFO: [Project 1-461] DRC finished with 0 Errors\r |
| 33 | INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.\r |
| 34 | \r |
| 35 | Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824\r |
| 36 | \r |
| 37 | Starting Cache Timing Information Task\r |
| 38 | INFO: [Timing 38-35] Done setting XDC timing constraints.\r |
| 39 | Ending Cache Timing Information Task | Checksum: 686e1c75\r |
| 40 | \r |
| 41 | Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363\r |
| 42 | \r |
| 43 | Starting Logic Optimization Task\r |
| 44 | \r |
| 45 | Phase 1 Retarget\r |
| 46 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r |
| 47 | INFO: [Opt 31-49] Retargeted 0 cell(s).\r |
| 48 | Phase 1 Retarget | Checksum: 686e1c75\r |
| 49 | \r |
| 50 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 51 | INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells\r |
| 52 | \r |
| 53 | Phase 2 Constant propagation\r |
| 54 | INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r |
| 55 | Phase 2 Constant propagation | Checksum: 686e1c75\r |
| 56 | \r |
| 57 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 58 | INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells\r |
| 59 | \r |
| 60 | Phase 3 Sweep\r |
| 61 | Phase 3 Sweep | Checksum: 686e1c75\r |
| 62 | \r |
| 63 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 64 | INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells\r |
| 65 | \r |
| 66 | Phase 4 BUFG optimization\r |
| 67 | Phase 4 BUFG optimization | Checksum: 686e1c75\r |
| 68 | \r |
| 69 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 70 | INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.\r |
| 71 | \r |
| 72 | Phase 5 Shift Register Optimization\r |
| 73 | INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs\r |
| 74 | Phase 5 Shift Register Optimization | Checksum: 686e1c75\r |
| 75 | \r |
| 76 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 77 | INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells\r |
| 78 | \r |
| 79 | Phase 6 Post Processing Netlist\r |
| 80 | Phase 6 Post Processing Netlist | Checksum: 686e1c75\r |
| 81 | \r |
| 82 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 83 | INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells\r |
| 84 | Opt_design Change Summary\r |
| 85 | =========================\r |
| 86 | \r |
| 87 | \r |
| 88 | -------------------------------------------------------------------------------------------------------------------------\r |
| 89 | | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |\r |
| 90 | -------------------------------------------------------------------------------------------------------------------------\r |
| 91 | | Retarget | 0 | 0 | 0 |\r |
| 92 | | Constant propagation | 0 | 0 | 0 |\r |
| 93 | | Sweep | 0 | 0 | 0 |\r |
| 94 | | BUFG optimization | 0 | 0 | 0 |\r |
| 95 | | Shift Register Optimization | 0 | 0 | 0 |\r |
| 96 | | Post Processing Netlist | 0 | 0 | 0 |\r |
| 97 | -------------------------------------------------------------------------------------------------------------------------\r |
| 98 | \r |
| 99 | \r |
| 100 | \r |
| 101 | Starting Connectivity Check Task\r |
| 102 | \r |
| 103 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 104 | Ending Logic Optimization Task | Checksum: 686e1c75\r |
| 105 | \r |
| 106 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781\r |
| 107 | \r |
| 108 | Starting Power Optimization Task\r |
| 109 | INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.\r |
| 110 | Ending Power Optimization Task | Checksum: 686e1c75\r |
| 111 | \r |
| 112 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 113 | \r |
| 114 | Starting Final Cleanup Task\r |
| 115 | Ending Final Cleanup Task | Checksum: 686e1c75\r |
| 116 | \r |
| 117 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 118 | \r |
| 119 | Starting Netlist Obfuscation Task\r |
| 120 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 121 | Ending Netlist Obfuscation Task | Checksum: 686e1c75\r |
| 122 | \r |
| 123 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 124 | INFO: [Common 17-83] Releasing license: Implementation\r |
| 125 | 21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r |
| 126 | opt_design completed successfully\r |
| 127 | opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559\r |
| 128 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r |
| 129 | WARNING: [Constraints 18-5210] No constraints selected for write.\r |
| 130 | Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.\r |
| 131 | INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated.\r |
| 132 | INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r |
| 133 | Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r |
| 134 | INFO: [IP_Flow 19-234] Refreshing IP repositories\r |
| 135 | INFO: [IP_Flow 19-1704] No user IP repositories specified\r |
| 136 | INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'.\r |
| 137 | INFO: [DRC 23-27] Running DRC with 2 threads\r |
| 138 | INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt.\r |
| 139 | report_drc completed successfully\r |
| 140 | Command: place_design\r |
| 141 | Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r |
| 142 | INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r |
| 143 | INFO: [DRC 23-27] Running DRC with 2 threads\r |
| 144 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r |
| 145 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r |
| 146 | Running DRC as a precondition to command place_design\r |
| 147 | INFO: [DRC 23-27] Running DRC with 2 threads\r |
| 148 | INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r |
| 149 | INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r |
| 150 | \r |
| 151 | Starting Placer Task\r |
| 152 | INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs\r |
| 153 | \r |
| 154 | Phase 1 Placer Initialization\r |
| 155 | \r |
| 156 | Phase 1.1 Placer Initialization Netlist Sorting\r |
| 157 | Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000\r |
| 158 | Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000\r |
| 159 | \r |
| 160 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000\r |
| 161 | Phase 1 Placer Initialization | Checksum: 00000000\r |
| 162 | \r |
| 163 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000\r |
| 164 | ERROR: [Place 30-494] The design is empty\r |
| 165 | Resolution: Check if opt_design has removed all the leaf cells of your design. Check whether you have instantiated and connected all of the top level ports.\r |
| 166 | Ending Placer Task | Checksum: 00000000\r |
| 167 | \r |
| 168 | Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000\r |
| 169 | INFO: [Common 17-83] Releasing license: Implementation\r |
| 170 | 37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.\r |
| 171 | place_design failed\r |
| 172 | ERROR: [Common 17-69] Command failed: Placer could not place all instances\r |
| 173 | INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019...\r |