esdi.runs/impl_1/runme.log

   1
   2 *** Running vivado
   3     with args -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace
   4
   5
   6 ****** Vivado v2019.1 (64-bit)
   7   **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
   8   **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
   9     ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
  10
  11 source esdi_ctl_phy.tcl -notrace
  12 Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1
  13 Design is defaulting to srcset: sources_1
  14 Design is defaulting to constrset: constrs_1
  15 INFO: [Device 21-403] Loading part xc7z007sclg225-1
  16 INFO: [Project 1-479] Netlist was created with Vivado 2019.1
  17 INFO: [Project 1-570] Preparing netlist for logic optimization
  18 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000
  19 INFO: [Project 1-111] Unisim Transformation Summary:
  20 No Unisim elements were transformed.
  21
  22 4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
  23 link_design completed successfully
  24 link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582
  25 Command: opt_design
  26 Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
  27 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
  28 Running DRC as a precondition to command opt_design
  29
  30 Starting DRC Task
  31 INFO: [DRC 23-27] Running DRC with 2 threads
  32 INFO: [Project 1-461] DRC finished with 0 Errors
  33 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
  34
  35 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824
  36
  37 Starting Cache Timing Information Task
  38 INFO: [Timing 38-35] Done setting XDC timing constraints.
  39 Ending Cache Timing Information Task | Checksum: 686e1c75
  40
  41 Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363
  42
  43 Starting Logic Optimization Task
  44
  45 Phase 1 Retarget
  46 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  47 INFO: [Opt 31-49] Retargeted 0 cell(s).
  48 Phase 1 Retarget | Checksum: 686e1c75
  49
  50 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781
  51 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
  52
  53 Phase 2 Constant propagation
  54 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
  55 Phase 2 Constant propagation | Checksum: 686e1c75
  56
  57 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781
  58 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
  59
  60 Phase 3 Sweep
  61 Phase 3 Sweep | Checksum: 686e1c75
  62
  63 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781
  64 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
  65
  66 Phase 4 BUFG optimization
  67 Phase 4 BUFG optimization | Checksum: 686e1c75
  68
  69 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781
  70 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
  71
  72 Phase 5 Shift Register Optimization
  73 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
  74 Phase 5 Shift Register Optimization | Checksum: 686e1c75
  75
  76 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781
  77 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
  78
  79 Phase 6 Post Processing Netlist
  80 Phase 6 Post Processing Netlist | Checksum: 686e1c75
  81
  82 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781
  83 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
  84 Opt_design Change Summary
  85 =========================
  86
  87
  88 -------------------------------------------------------------------------------------------------------------------------
  89 |  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
  90 -------------------------------------------------------------------------------------------------------------------------
  91 |  Retarget                     |               0  |               0  |                                              0  |
  92 |  Constant propagation         |               0  |               0  |                                              0  |
  93 |  Sweep                        |               0  |               0  |                                              0  |
  94 |  BUFG optimization            |               0  |               0  |                                              0  |
  95 |  Shift Register Optimization  |               0  |               0  |                                              0  |
  96 |  Post Processing Netlist      |               0  |               0  |                                              0  |
  97 -------------------------------------------------------------------------------------------------------------------------
  98
  99
 100
 101 Starting Connectivity Check Task
 102
 103 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
 104 Ending Logic Optimization Task | Checksum: 686e1c75
 105
 106 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781
 107
 108 Starting Power Optimization Task
 109 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
 110 Ending Power Optimization Task | Checksum: 686e1c75
 111
 112 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000
 113
 114 Starting Final Cleanup Task
 115 Ending Final Cleanup Task | Checksum: 686e1c75
 116
 117 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000
 118
 119 Starting Netlist Obfuscation Task
 120 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
 121 Ending Netlist Obfuscation Task | Checksum: 686e1c75
 122
 123 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
 124 INFO: [Common 17-83] Releasing license: Implementation
 125 21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 126 opt_design completed successfully
 127 opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559
 128 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
 129 WARNING: [Constraints 18-5210] No constraints selected for write.
 130 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 131 INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated.
 132 INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx
 133 Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx
 134 INFO: [IP_Flow 19-234] Refreshing IP repositories
 135 INFO: [IP_Flow 19-1704] No user IP repositories specified
 136 INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'.
 137 INFO: [DRC 23-27] Running DRC with 2 threads
 138 INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt.
 139 report_drc completed successfully
 140 Command: place_design
 141 Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
 142 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
 143 INFO: [DRC 23-27] Running DRC with 2 threads
 144 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 145 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 146 Running DRC as a precondition to command place_design
 147 INFO: [DRC 23-27] Running DRC with 2 threads
 148 INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
 149 INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
 150
 151 Starting Placer Task
 152 INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
 153
 154 Phase 1 Placer Initialization
 155
 156 Phase 1.1 Placer Initialization Netlist Sorting
 157 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000
 158 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000
 159
 160 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000
 161 Phase 1 Placer Initialization | Checksum: 00000000
 162
 163 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000
 164 ERROR: [Place 30-494] The design is empty
 165 Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.
 166 Ending Placer Task | Checksum: 00000000
 167
 168 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000
 169 INFO: [Common 17-83] Releasing license: Implementation
 170 37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
 171 place_design failed
 172 ERROR: [Common 17-69] Command failed: Placer could not place all instances
 173 INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019...