initial

[esdi.git] / esdi.runs / impl_1 / runme.log

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*** Running vivado\r
    with args -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace\r
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****** Vivado v2019.1 (64-bit)\r
  **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019\r
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019\r
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
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source esdi_ctl_phy.tcl -notrace\r
Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
Design is defaulting to srcset: sources_1\r
Design is defaulting to constrset: constrs_1\r
INFO: [Device 21-403] Loading part xc7z007sclg225-1\r
INFO: [Project 1-479] Netlist was created with Vivado 2019.1\r
INFO: [Project 1-570] Preparing netlist for logic optimization\r
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000\r
INFO: [Project 1-111] Unisim Transformation Summary:\r
No Unisim elements were transformed.\r
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4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
link_design completed successfully\r
link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582\r
Command: opt_design\r
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r
Running DRC as a precondition to command opt_design\r
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Starting DRC Task\r
INFO: [DRC 23-27] Running DRC with 2 threads\r
INFO: [Project 1-461] DRC finished with 0 Errors\r
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.\r
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Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824\r
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Starting Cache Timing Information Task\r
INFO: [Timing 38-35] Done setting XDC timing constraints.\r
Ending Cache Timing Information Task | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363\r
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Starting Logic Optimization Task\r
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Phase 1 Retarget\r
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
INFO: [Opt 31-49] Retargeted 0 cell(s).\r
Phase 1 Retarget | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells\r
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Phase 2 Constant propagation\r
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
Phase 2 Constant propagation | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells\r
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Phase 3 Sweep\r
Phase 3 Sweep | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells\r
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Phase 4 BUFG optimization\r
Phase 4 BUFG optimization | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.\r
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Phase 5 Shift Register Optimization\r
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs\r
Phase 5 Shift Register Optimization | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells\r
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Phase 6 Post Processing Netlist\r
Phase 6 Post Processing Netlist | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells\r
Opt_design Change Summary\r
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-------------------------------------------------------------------------------------------------------------------------\r
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |\r
-------------------------------------------------------------------------------------------------------------------------\r
|  Retarget                     |               0  |               0  |                                              0  |\r
|  Constant propagation         |               0  |               0  |                                              0  |\r
|  Sweep                        |               0  |               0  |                                              0  |\r
|  BUFG optimization            |               0  |               0  |                                              0  |\r
|  Shift Register Optimization  |               0  |               0  |                                              0  |\r
|  Post Processing Netlist      |               0  |               0  |                                              0  |\r
-------------------------------------------------------------------------------------------------------------------------\r
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Starting Connectivity Check Task\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
Ending Logic Optimization Task | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
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Starting Power Optimization Task\r
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.\r
Ending Power Optimization Task | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
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Starting Final Cleanup Task\r
Ending Final Cleanup Task | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
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Starting Netlist Obfuscation Task\r
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
Ending Netlist Obfuscation Task | Checksum: 686e1c75\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
INFO: [Common 17-83] Releasing license: Implementation\r
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
opt_design completed successfully\r
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559\r
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
WARNING: [Constraints 18-5210] No constraints selected for write.\r
Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.\r
INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated.\r
INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r
Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r
INFO: [IP_Flow 19-234] Refreshing IP repositories\r
INFO: [IP_Flow 19-1704] No user IP repositories specified\r
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'.\r
INFO: [DRC 23-27] Running DRC with 2 threads\r
INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt.\r
report_drc completed successfully\r
Command: place_design\r
Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r
INFO: [DRC 23-27] Running DRC with 2 threads\r
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r
Running DRC as a precondition to command place_design\r
INFO: [DRC 23-27] Running DRC with 2 threads\r
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r
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Starting Placer Task\r
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs\r
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Phase 1 Placer Initialization\r
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Phase 1.1 Placer Initialization Netlist Sorting\r
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
Phase 1 Placer Initialization | Checksum: 00000000\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
ERROR: [Place 30-494] The design is empty\r
Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.\r
Ending Placer Task | Checksum: 00000000\r
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Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
INFO: [Common 17-83] Releasing license: Implementation\r
37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.\r
place_design failed\r
ERROR: [Common 17-69] Command failed: Placer could not place all instances\r
INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019...\r