esdi.runs/synth_1/esdi_ctl_phy.tcl

   1 #
   2 # Synthesis run script generated by Vivado
   3 #
   4
   5 set TIME_start [clock seconds]
   6 proc create_report { reportName command } {
   7   set status "."
   8   append status $reportName ".fail"
   9   if { [file exists $status] } {
  10     eval file delete [glob $status]
  11   }
  12   send_msg_id runtcl-4 info "Executing : $command"
  13   set retval [eval catch { $command } msg]
  14   if { $retval != 0 } {
  15     set fp [open $status w]
  16     close $fp
  17     send_msg_id runtcl-5 warning "$msg"
  18   }
  19 }
  20 create_project -in_memory -part xc7z007sclg225-1
  21
  22 set_param project.singleFileAddWarning.threshold 0
  23 set_param project.compositeFile.enableAutoGeneration 0
  24 set_param synth.vivado.isSynthRun true
  25 set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project]
  26 set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project]
  27 set_property default_lib xil_defaultlib [current_project]
  28 set_property target_language Verilog [current_project]
  29 set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project]
  30 set_property board_part em.avnet.com:minized:part0:1.2 [current_project]
  31 set_property ip_output_repo s:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project]
  32 set_property ip_cache_permissions {read write} [current_project]
  33 read_verilog -library xil_defaultlib S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v
  34 # Mark all dcp files as not used in implementation to prevent them from being
  35 # stitched into the results of this synthesis run. Any black boxes in the
  36 # design are intentionally left as such for best results. Dcp files will be
  37 # stitched into the design at a later time, either when this synthesis run is
  38 # opened, or when it is stitched into a dependent implementation run.
  39 foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  40   set_property used_in_implementation false $dcp
  41 }
  42 set_param ips.enableIPCacheLiteLoad 1
  43 close [open __synthesis_is_running__ w]
  44
  45 synth_design -top esdi_ctl_phy -part xc7z007sclg225-1
  46
  47
  48 # disable binary constraint mode for synth run checkpoints
  49 set_param constraints.enableBinaryConstraints false
  50 write_checkpoint -force -noxdef esdi_ctl_phy.dcp
  51 create_report "synth_1_synth_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb"
  52 file delete __synthesis_is_running__
  53 close [open __synthesis_is_complete__ w]