esdi.runs/synth_1/esdi_ctl_phy.vds

   1 #-----------------------------------------------------------
   2 # Vivado v2019.1 (64-bit)
   3 # SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
   4 # IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
   5 # Start of session at: Tue Aug 13 10:38:50 2019
   6 # Process ID: 20424
   7 # Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1
   8 # Command line: vivado.exe -log esdi_ctl_phy.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl
   9 # Log file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.vds
  10 # Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1\vivado.jou
  11 #-----------------------------------------------------------
  12 source esdi_ctl_phy.tcl -notrace
  13 Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1
  14 Starting synth_design
  15 Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s'
  16 INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s'
  17 INFO: Launching helper process for spawning children vivado processes
  18 INFO: Helper process launched with PID 18332
  19 ---------------------------------------------------------------------------------
  20 Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551
  21 ---------------------------------------------------------------------------------
  22 INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
  23 INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
  24 WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
  25 ---------------------------------------------------------------------------------
  26 Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  27 ---------------------------------------------------------------------------------
  28 ---------------------------------------------------------------------------------
  29 Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  30 ---------------------------------------------------------------------------------
  31 ---------------------------------------------------------------------------------
  32 Start Loading Part and Timing Information
  33 ---------------------------------------------------------------------------------
  34 Loading part: xc7z007sclg225-1
  35 ---------------------------------------------------------------------------------
  36 Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
  37 ---------------------------------------------------------------------------------
  38 INFO: [Device 21-403] Loading part xc7z007sclg225-1
  39 ---------------------------------------------------------------------------------
  40 Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852
  41 ---------------------------------------------------------------------------------
  42
  43 Report RTL Partitions:
  44 +-+--------------+------------+----------+
  45 | |RTL Partition |Replication |Instances |
  46 +-+--------------+------------+----------+
  47 +-+--------------+------------+----------+
  48 No constraint files found.
  49 ---------------------------------------------------------------------------------
  50 Start RTL Component Statistics
  51 ---------------------------------------------------------------------------------
  52 Detailed RTL Component Info :
  53 ---------------------------------------------------------------------------------
  54 Finished RTL Component Statistics
  55 ---------------------------------------------------------------------------------
  56 ---------------------------------------------------------------------------------
  57 Start RTL Hierarchical Component Statistics
  58 ---------------------------------------------------------------------------------
  59 Hierarchical RTL Component report
  60 ---------------------------------------------------------------------------------
  61 Finished RTL Hierarchical Component Statistics
  62 ---------------------------------------------------------------------------------
  63 ---------------------------------------------------------------------------------
  64 Start Part Resource Summary
  65 ---------------------------------------------------------------------------------
  66 Part Resources:
  67 DSPs: 66 (col length:40)
  68 BRAMs: 100 (col length: RAMB18 40 RAMB36 20)
  69 ---------------------------------------------------------------------------------
  70 Finished Part Resource Summary
  71 ---------------------------------------------------------------------------------
  72 No constraint files found.
  73 ---------------------------------------------------------------------------------
  74 Start Cross Boundary and Area Optimization
  75 ---------------------------------------------------------------------------------
  76 Warning: Parallel synthesis criteria is not met
  77 WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
  78 ---------------------------------------------------------------------------------
  79 Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
  80 ---------------------------------------------------------------------------------
  81
  82 Report RTL Partitions:
  83 +-+--------------+------------+----------+
  84 | |RTL Partition |Replication |Instances |
  85 +-+--------------+------------+----------+
  86 +-+--------------+------------+----------+
  87 No constraint files found.
  88 ---------------------------------------------------------------------------------
  89 Start Timing Optimization
  90 ---------------------------------------------------------------------------------
  91 ---------------------------------------------------------------------------------
  92 Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
  93 ---------------------------------------------------------------------------------
  94
  95 Report RTL Partitions:
  96 +-+--------------+------------+----------+
  97 | |RTL Partition |Replication |Instances |
  98 +-+--------------+------------+----------+
  99 +-+--------------+------------+----------+
 100 ---------------------------------------------------------------------------------
 101 Start Technology Mapping
 102 ---------------------------------------------------------------------------------
 103 ---------------------------------------------------------------------------------
 104 Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
 105 ---------------------------------------------------------------------------------
 106
 107 Report RTL Partitions:
 108 +-+--------------+------------+----------+
 109 | |RTL Partition |Replication |Instances |
 110 +-+--------------+------------+----------+
 111 +-+--------------+------------+----------+
 112 ---------------------------------------------------------------------------------
 113 Start IO Insertion
 114 ---------------------------------------------------------------------------------
 115 ---------------------------------------------------------------------------------
 116 Start Flattening Before IO Insertion
 117 ---------------------------------------------------------------------------------
 118 ---------------------------------------------------------------------------------
 119 Finished Flattening Before IO Insertion
 120 ---------------------------------------------------------------------------------
 121 ---------------------------------------------------------------------------------
 122 Start Final Netlist Cleanup
 123 ---------------------------------------------------------------------------------
 124 ---------------------------------------------------------------------------------
 125 Finished Final Netlist Cleanup
 126 ---------------------------------------------------------------------------------
 127 ---------------------------------------------------------------------------------
 128 Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 129 ---------------------------------------------------------------------------------
 130
 131 Report Check Netlist:
 132 +------+------------------+-------+---------+-------+------------------+
 133 |      |Item              |Errors |Warnings |Status |Description       |
 134 +------+------------------+-------+---------+-------+------------------+
 135 |1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
 136 +------+------------------+-------+---------+-------+------------------+
 137 ---------------------------------------------------------------------------------
 138 Start Renaming Generated Instances
 139 ---------------------------------------------------------------------------------
 140 ---------------------------------------------------------------------------------
 141 Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 142 ---------------------------------------------------------------------------------
 143
 144 Report RTL Partitions:
 145 +-+--------------+------------+----------+
 146 | |RTL Partition |Replication |Instances |
 147 +-+--------------+------------+----------+
 148 +-+--------------+------------+----------+
 149 ---------------------------------------------------------------------------------
 150 Start Rebuilding User Hierarchy
 151 ---------------------------------------------------------------------------------
 152 ---------------------------------------------------------------------------------
 153 Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 154 ---------------------------------------------------------------------------------
 155 ---------------------------------------------------------------------------------
 156 Start Renaming Generated Ports
 157 ---------------------------------------------------------------------------------
 158 ---------------------------------------------------------------------------------
 159 Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 160 ---------------------------------------------------------------------------------
 161 ---------------------------------------------------------------------------------
 162 Start Handling Custom Attributes
 163 ---------------------------------------------------------------------------------
 164 ---------------------------------------------------------------------------------
 165 Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 166 ---------------------------------------------------------------------------------
 167 ---------------------------------------------------------------------------------
 168 Start Renaming Generated Nets
 169 ---------------------------------------------------------------------------------
 170 ---------------------------------------------------------------------------------
 171 Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 172 ---------------------------------------------------------------------------------
 173 ---------------------------------------------------------------------------------
 174 Start Writing Synthesis Report
 175 ---------------------------------------------------------------------------------
 176
 177 Report BlackBoxes:
 178 +-+--------------+----------+
 179 | |BlackBox name |Instances |
 180 +-+--------------+----------+
 181 +-+--------------+----------+
 182
 183 Report Cell Usage:
 184 +------+-------------+------+
 185 |      |Cell         |Count |
 186 +------+-------------+------+
 187 |1     |esdi_ctl_phy |     1|
 188 +------+-------------+------+
 189
 190 Report Instance Areas:
 191 +------+---------+-------+------+
 192 |      |Instance |Module |Cells |
 193 +------+---------+-------+------+
 194 |1     |top      |       |     0|
 195 +------+---------+-------+------+
 196 ---------------------------------------------------------------------------------
 197 Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 198 ---------------------------------------------------------------------------------
 199 Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
 200 Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 201 Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
 202 INFO: [Project 1-571] Translating synthesized netlist
 203 INFO: [Project 1-570] Preparing netlist for logic optimization
 204 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 205 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
 206 INFO: [Project 1-111] Unisim Transformation Summary:
 207 No Unisim elements were transformed.
 208
 209 INFO: [Common 17-83] Releasing license: Synthesis
 210 9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
 211 synth_design completed successfully
 212 synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191
 213 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
 214 WARNING: [Constraints 18-5210] No constraints selected for write.
 215 Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
 216 INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated.
 217 INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb
 218 INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019...