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diff --git a/esdi.cache/wt/gui_handlers.wdf b/esdi.cache/wt/gui_handlers.wdf
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diff --git a/esdi.cache/wt/java_command_handlers.wdf b/esdi.cache/wt/java_command_handlers.wdf
new file mode 100644 (file)
index 0000000..78e1f12
--- /dev/null
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diff --git a/esdi.cache/wt/project.wpc b/esdi.cache/wt/project.wpc
new file mode 100644 (file)
index 0000000..d9ddfe2
--- /dev/null
+++ b/esdi.cache/wt/project.wpc
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diff --git a/esdi.cache/wt/synthesis.wdf b/esdi.cache/wt/synthesis.wdf
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diff --git a/esdi.cache/wt/synthesis_details.wdf b/esdi.cache/wt/synthesis_details.wdf
new file mode 100644 (file)
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diff --git a/esdi.cache/wt/webtalk_pa.xml b/esdi.cache/wt/webtalk_pa.xml
new file mode 100644 (file)
index 0000000..7985efd
--- /dev/null
+++ b/esdi.cache/wt/webtalk_pa.xml
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8" ?>\r
+<document>\r
+<!--The data in this file is primarily intended for consumption by Xilinx tools.\r
+The structure and the elements are likely to change over the next few releases.\r
+This means code written to parse this file will need to be revisited each subsequent release.-->\r
+<application name="pa" timeStamp="Tue Aug 13 10:39:21 2019">\r
+<section name="Project Information" visible="false">\r
+<property name="ProjectID" value="e27f0447273746a49069d8f4f202ad6d" type="ProjectID"/>\r
+<property name="ProjectIteration" value="2" type="ProjectIteration"/>\r
+</section>\r
+<section name="PlanAhead Usage" visible="true">\r
+<item name="Project Data">\r
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>\r
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>\r
+<property name="DesignMode" value="RTL" type="DesignMode"/>\r
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>\r
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>\r
+</item>\r
+<item name="Java Command Handlers">\r
+<property name="AddDesignTools" value="2" type="JavaHandler"/>\r
+<property name="CoreView" value="1" type="JavaHandler"/>\r
+<property name="LaunchXhubDownloader" value="1" type="JavaHandler"/>\r
+<property name="NewProject" value="1" type="JavaHandler"/>\r
+<property name="OpenProject" value="1" type="JavaHandler"/>\r
+<property name="RunImplementation" value="2" type="JavaHandler"/>\r
+<property name="RunSynthesis" value="1" type="JavaHandler"/>\r
+<property name="SimulationCompileLibraries" value="1" type="JavaHandler"/>\r
+<property name="ToolsSettings" value="7" type="JavaHandler"/>\r
+</item>\r
+<item name="Gui Handlers">\r
+<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>\r
+<property name="BaseDialog_OK" value="7" type="GuiHandlerData"/>\r
+<property name="BoardChooser_BOARD_TABLE" value="48" type="GuiHandlerData"/>\r
+<property name="BoardChooser_UPDATE_BOARD_REPOSITORIES" value="1" type="GuiHandlerData"/>\r
+<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="1" type="GuiHandlerData"/>\r
+<property name="FPGAChooser_FPGA_TABLE" value="1" type="GuiHandlerData"/>\r
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="3" type="GuiHandlerData"/>\r
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>\r
+<property name="GettingStartedView_CREATE_NEW_PROJECT" value="1" type="GuiHandlerData"/>\r
+<property name="GettingStartedView_OPEN_PROJECT" value="1" type="GuiHandlerData"/>\r
+<property name="HPopupTitle_CLOSE" value="1" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_CHECKPOINT" value="3" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_DESIGN_HUBS" value="5" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_EDIT" value="14" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_EXPORT" value="4" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_FILE" value="10" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_FLOW" value="29" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_HELP" value="22" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_IP" value="3" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_PROJECT" value="4" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_REPORTS" value="20" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_SETTINGS" value="3" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_TEXT_EDITOR" value="4" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_TOOLS" value="40" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_VIEW" value="21" type="GuiHandlerData"/>\r
+<property name="MainMenuMgr_WINDOW" value="24" type="GuiHandlerData"/>\r
+<property name="MainToolbarMgr_RUN" value="2" type="GuiHandlerData"/>\r
+<property name="MainWinMenuMgr_LAYOUT" value="15" type="GuiHandlerData"/>\r
+<property name="NewProjectWizard_DO_NOT_SPECIFY_SOURCES_AT_THIS_TIME" value="2" type="GuiHandlerData"/>\r
+<property name="PACommandNames_ADD_DESIGN_TOOLS" value="2" type="GuiHandlerData"/>\r
+<property name="PACommandNames_DOC_AND_TUTORIAL_HELP" value="1" type="GuiHandlerData"/>\r
+<property name="PACommandNames_QUICK_HELP" value="1" type="GuiHandlerData"/>\r
+<property name="PACommandNames_RUN_IMPLEMENTATION" value="1" type="GuiHandlerData"/>\r
+<property name="PACommandNames_RUN_SYNTHESIS" value="1" type="GuiHandlerData"/>\r
+<property name="PACommandNames_SIMULATION_COMPILE_LIBRARIES" value="1" type="GuiHandlerData"/>\r
+<property name="PACommandNames_SIMULATION_SETTINGS" value="1" type="GuiHandlerData"/>\r
+<property name="ProgressDialog_CANCEL" value="1" type="GuiHandlerData"/>\r
+<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="2" type="GuiHandlerData"/>\r
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>\r
+<property name="ProjectSettingsSimulationPanel_TABBED_PANE" value="1" type="GuiHandlerData"/>\r
+<property name="ProjectSettingsSimulationPanel_TARGET_SIMULATOR" value="3" type="GuiHandlerData"/>\r
+<property name="RDICommands_CUSTOM_COMMANDS" value="6" type="GuiHandlerData"/>\r
+<property name="RDICommands_SETTINGS" value="6" type="GuiHandlerData"/>\r
+<property name="SettingsDialog_OPTIONS_TREE" value="2" type="GuiHandlerData"/>\r
+<property name="SettingsDialog_PROJECT_TREE" value="7" type="GuiHandlerData"/>\r
+<property name="SettingsProjectGeneralPage_CHOOSE_DEVICE_FOR_YOUR_PROJECT" value="1" type="GuiHandlerData"/>\r
+<property name="SimulationCompileLibrariesDialog_COMPILE" value="1" type="GuiHandlerData"/>\r
+<property name="SimulationCompileLibrariesDialog_SIMULATOR" value="1" type="GuiHandlerData"/>\r
+</item>\r
+</section>\r
+</application>\r
+</document>\r

diff --git a/esdi.hw/esdi.lpr b/esdi.hw/esdi.lpr
new file mode 100644 (file)
index 0000000..8d9c70d
--- /dev/null
+++ b/esdi.hw/esdi.lpr
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<!-- Product Version: Vivado v2019.1 (64-bit)                     -->\r
+<!--                                                              -->\r
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.        -->\r
+\r
+<labtools version="1" minor="0">\r
+  <HWSession Dir="hw_1" File="hw.xml"/>\r
+</labtools>\r

diff --git a/esdi.hw/hw_1/hw.xml b/esdi.hw/hw_1/hw.xml
new file mode 100644 (file)
index 0000000..cd0a367
--- /dev/null
+++ b/esdi.hw/hw_1/hw.xml
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<!-- Product Version: Vivado v2019.1 (64-bit)                     -->\r
+<!--                                                              -->\r
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.        -->\r
+\r
+<hwsession version="1" minor="2">\r
+  <device name="xc7z007s_1" gui_info="dashboard1=hw_ila_1[xc7z007s_1/hw_ila_1/Settings=ILA_SETTINGS_1;xc7z007s_1/hw_ila_1/Waveform=ILA_WAVE_1;xc7z007s_1/hw_ila_1/Capture Setup=ILA_CAPTURE_1;xc7z007s_1/hw_ila_1/Status=ILA_STATUS_1;xc7z007s_1/hw_ila_1/Trigger Setup=ILA_TRIGGER_1;],dashboard2=hw_ila_2[xc7z007s_1/hw_ila_2/Capture Setup=ILA_CAPTURE_1;xc7z007s_1/hw_ila_2/Settings=ILA_SETTINGS_1;xc7z007s_1/hw_ila_2/Trigger Setup=ILA_TRIGGER_1;xc7z007s_1/hw_ila_2/Waveform=ILA_WAVE_1;xc7z007s_1/hw_ila_2/Status=ILA_STATUS_1;]"/>\r
+  <ObjectList object_type="hw_ila" gui_info="">\r
+    <Object name="" gui_info="">\r
+      <Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>\r
+      <Properties Property="CORE_REFRESH_RATE_MS" value="500"/>\r
+    </Object>\r
+  </ObjectList>\r
+  <probeset name="hw project" active="false"/>\r
+</hwsession>\r

diff --git a/esdi.ip_user_files/README.txt b/esdi.ip_user_files/README.txt
new file mode 100644 (file)
index 0000000..9015e04
--- /dev/null
+++ b/esdi.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.\r

diff --git a/esdi.runs/.jobs/vrs_config_1.xml b/esdi.runs/.jobs/vrs_config_1.xml
new file mode 100644 (file)
index 0000000..afd27fb
--- /dev/null
+++ b/esdi.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>\r
+<Runs Version="1" Minor="0">\r
+       <Run Id="synth_1" LaunchDir="S:/vivado-projects/esdi/esdi/esdi.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>\r
+       <Parameters>\r
+               <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>\r
+       </Parameters>\r
+</Runs>\r
+\r

diff --git a/esdi.runs/.jobs/vrs_config_2.xml b/esdi.runs/.jobs/vrs_config_2.xml
new file mode 100644 (file)
index 0000000..897bfb4
--- /dev/null
+++ b/esdi.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,8 @@
+<?xml version="1.0"?>\r
+<Runs Version="1" Minor="0">\r
+       <Run Id="impl_1" LaunchDir="S:/vivado-projects/esdi/esdi/esdi.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>\r
+       <Parameters>\r
+               <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>\r
+       </Parameters>\r
+</Runs>\r
+\r

diff --git a/esdi.runs/impl_1/.Vivado_Implementation.queue.rst b/esdi.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/impl_1/.init_design.begin.rst b/esdi.runs/impl_1/.init_design.begin.rst
new file mode 100644 (file)
index 0000000..1e7d57c
--- /dev/null
+++ b/esdi.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>\r
+<ProcessHandle Version="1" Minor="0">\r
+    <Process Command=".planAhead." Owner="kremlin" Host="KREMLINMACHINE" Pid="13936">\r
+    </Process>\r
+</ProcessHandle>\r

diff --git a/esdi.runs/impl_1/.init_design.end.rst b/esdi.runs/impl_1/.init_design.end.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/impl_1/.opt_design.begin.rst b/esdi.runs/impl_1/.opt_design.begin.rst
new file mode 100644 (file)
index 0000000..1e7d57c
--- /dev/null
+++ b/esdi.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>\r
+<ProcessHandle Version="1" Minor="0">\r
+    <Process Command=".planAhead." Owner="kremlin" Host="KREMLINMACHINE" Pid="13936">\r
+    </Process>\r
+</ProcessHandle>\r

diff --git a/esdi.runs/impl_1/.opt_design.end.rst b/esdi.runs/impl_1/.opt_design.end.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/impl_1/.place_design.begin.rst b/esdi.runs/impl_1/.place_design.begin.rst
new file mode 100644 (file)
index 0000000..1e7d57c
--- /dev/null
+++ b/esdi.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>\r
+<ProcessHandle Version="1" Minor="0">\r
+    <Process Command=".planAhead." Owner="kremlin" Host="KREMLINMACHINE" Pid="13936">\r
+    </Process>\r
+</ProcessHandle>\r

diff --git a/esdi.runs/impl_1/.place_design.error.rst b/esdi.runs/impl_1/.place_design.error.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/impl_1/.vivado.begin.rst b/esdi.runs/impl_1/.vivado.begin.rst
new file mode 100644 (file)
index 0000000..b16ec11
--- /dev/null
+++ b/esdi.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>\r
+<ProcessHandle Version="1" Minor="0">\r
+    <Process Command="vivado.bat" Owner="kremlin" Host="KREMLINMACHINE" Pid="20216" HostCore="24" HostMemory="034235731968">\r
+    </Process>\r
+</ProcessHandle>\r

diff --git a/esdi.runs/impl_1/.vivado.error.rst b/esdi.runs/impl_1/.vivado.error.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/impl_1/ISEWrap.js b/esdi.runs/impl_1/ISEWrap.js
new file mode 100644 (file)
index 0000000..3e83de1
--- /dev/null
+++ b/esdi.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+              ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+                           "\" Owner=\"" + ISEUser + 
+                           "\" Host=\"" + ISEHost + 
+                           "\" Pid=\"" + ISEPid +
+                           "\" HostCore=\"" + ISEHOSTCORE +
+                           "\" HostMemory=\"" + ISEMEMTOTAL +
+                           "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {\r
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);\r
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}

diff --git a/esdi.runs/impl_1/ISEWrap.sh b/esdi.runs/impl_1/ISEWrap.sh
new file mode 100644 (file)
index 0000000..f679f2e
--- /dev/null
+++ b/esdi.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+

diff --git a/esdi.runs/impl_1/esdi_ctl_phy.tcl b/esdi.runs/impl_1/esdi_ctl_phy.tcl
new file mode 100644 (file)
index 0000000..1464cec
--- /dev/null
+++ b/esdi.runs/impl_1/esdi_ctl_phy.tcl
@@ -0,0 +1,153 @@
+# \r
+# Report generation script generated by Vivado\r
+# \r
+\r
+proc create_report { reportName command } {\r
+  set status "."\r
+  append status $reportName ".fail"\r
+  if { [file exists $status] } {\r
+    eval file delete [glob $status]\r
+  }\r
+  send_msg_id runtcl-4 info "Executing : $command"\r
+  set retval [eval catch { $command } msg]\r
+  if { $retval != 0 } {\r
+    set fp [open $status w]\r
+    close $fp\r
+    send_msg_id runtcl-5 warning "$msg"\r
+  }\r
+}\r
+proc start_step { step } {\r
+  set stopFile ".stop.rst"\r
+  if {[file isfile .stop.rst]} {\r
+    puts ""\r
+    puts "*** Halting run - EA reset detected ***"\r
+    puts ""\r
+    puts ""\r
+    return -code error\r
+  }\r
+  set beginFile ".$step.begin.rst"\r
+  set platform "$::tcl_platform(platform)"\r
+  set user "$::tcl_platform(user)"\r
+  set pid [pid]\r
+  set host ""\r
+  if { [string equal $platform unix] } {\r
+    if { [info exist ::env(HOSTNAME)] } {\r
+      set host $::env(HOSTNAME)\r
+    }\r
+  } else {\r
+    if { [info exist ::env(COMPUTERNAME)] } {\r
+      set host $::env(COMPUTERNAME)\r
+    }\r
+  }\r
+  set ch [open $beginFile w]\r
+  puts $ch "<?xml version=\"1.0\"?>"\r
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"\r
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"\r
+  puts $ch "    </Process>"\r
+  puts $ch "</ProcessHandle>"\r
+  close $ch\r
+}\r
+\r
+proc end_step { step } {\r
+  set endFile ".$step.end.rst"\r
+  set ch [open $endFile w]\r
+  close $ch\r
+}\r
+\r
+proc step_failed { step } {\r
+  set endFile ".$step.error.rst"\r
+  set ch [open $endFile w]\r
+  close $ch\r
+}\r
+\r
+\r
+start_step init_design\r
+set ACTIVE_STEP init_design\r
+set rc [catch {\r
+  create_msg_db init_design.pb\r
+  set_param chipscope.maxJobs 6\r
+  create_project -in_memory -part xc7z007sclg225-1\r
+  set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project]\r
+  set_property board_part em.avnet.com:minized:part0:1.2 [current_project]\r
+  set_property design_mode GateLvl [current_fileset]\r
+  set_param project.singleFileAddWarning.threshold 0\r
+  set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project]\r
+  set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project]\r
+  set_property ip_output_repo S:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project]\r
+  set_property ip_cache_permissions {read write} [current_project]\r
+  add_files -quiet S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp\r
+  link_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
+  close_msg_db -file init_design.pb\r
+} RESULT]\r
+if {$rc} {\r
+  step_failed init_design\r
+  return -code error $RESULT\r
+} else {\r
+  end_step init_design\r
+  unset ACTIVE_STEP \r
+}\r
+\r
+start_step opt_design\r
+set ACTIVE_STEP opt_design\r
+set rc [catch {\r
+  create_msg_db opt_design.pb\r
+  opt_design \r
+  write_checkpoint -force esdi_ctl_phy_opt.dcp\r
+  create_report "impl_1_opt_report_drc_0" "report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx"\r
+  close_msg_db -file opt_design.pb\r
+} RESULT]\r
+if {$rc} {\r
+  step_failed opt_design\r
+  return -code error $RESULT\r
+} else {\r
+  end_step opt_design\r
+  unset ACTIVE_STEP \r
+}\r
+\r
+start_step place_design\r
+set ACTIVE_STEP place_design\r
+set rc [catch {\r
+  create_msg_db place_design.pb\r
+  if { [llength [get_debug_cores -quiet] ] > 0 }  { \r
+    implement_debug_core \r
+  } \r
+  place_design \r
+  write_checkpoint -force esdi_ctl_phy_placed.dcp\r
+  create_report "impl_1_place_report_io_0" "report_io -file esdi_ctl_phy_io_placed.rpt"\r
+  create_report "impl_1_place_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_placed.rpt -pb esdi_ctl_phy_utilization_placed.pb"\r
+  create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file esdi_ctl_phy_control_sets_placed.rpt"\r
+  close_msg_db -file place_design.pb\r
+} RESULT]\r
+if {$rc} {\r
+  step_failed place_design\r
+  return -code error $RESULT\r
+} else {\r
+  end_step place_design\r
+  unset ACTIVE_STEP \r
+}\r
+\r
+start_step route_design\r
+set ACTIVE_STEP route_design\r
+set rc [catch {\r
+  create_msg_db route_design.pb\r
+  route_design \r
+  write_checkpoint -force esdi_ctl_phy_routed.dcp\r
+  create_report "impl_1_route_report_drc_0" "report_drc -file esdi_ctl_phy_drc_routed.rpt -pb esdi_ctl_phy_drc_routed.pb -rpx esdi_ctl_phy_drc_routed.rpx"\r
+  create_report "impl_1_route_report_methodology_0" "report_methodology -file esdi_ctl_phy_methodology_drc_routed.rpt -pb esdi_ctl_phy_methodology_drc_routed.pb -rpx esdi_ctl_phy_methodology_drc_routed.rpx"\r
+  create_report "impl_1_route_report_power_0" "report_power -file esdi_ctl_phy_power_routed.rpt -pb esdi_ctl_phy_power_summary_routed.pb -rpx esdi_ctl_phy_power_routed.rpx"\r
+  create_report "impl_1_route_report_route_status_0" "report_route_status -file esdi_ctl_phy_route_status.rpt -pb esdi_ctl_phy_route_status.pb"\r
+  create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -file esdi_ctl_phy_timing_summary_routed.rpt -pb esdi_ctl_phy_timing_summary_routed.pb -rpx esdi_ctl_phy_timing_summary_routed.rpx -warn_on_violation "\r
+  create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file esdi_ctl_phy_incremental_reuse_routed.rpt"\r
+  create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file esdi_ctl_phy_clock_utilization_routed.rpt"\r
+  create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file esdi_ctl_phy_bus_skew_routed.rpt -pb esdi_ctl_phy_bus_skew_routed.pb -rpx esdi_ctl_phy_bus_skew_routed.rpx"\r
+  close_msg_db -file route_design.pb\r
+} RESULT]\r
+if {$rc} {\r
+  write_checkpoint -force esdi_ctl_phy_routed_error.dcp\r
+  step_failed route_design\r
+  return -code error $RESULT\r
+} else {\r
+  end_step route_design\r
+  unset ACTIVE_STEP \r
+}\r
+\r

diff --git a/esdi.runs/impl_1/esdi_ctl_phy.vdi b/esdi.runs/impl_1/esdi_ctl_phy.vdi
new file mode 100644 (file)
index 0000000..389a74a
--- /dev/null
+++ b/esdi.runs/impl_1/esdi_ctl_phy.vdi
@@ -0,0 +1,174 @@
+#-----------------------------------------------------------
+# Vivado v2019.1 (64-bit)
+# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
+# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
+# Start of session at: Tue Aug 13 10:39:28 2019
+# Process ID: 13936
+# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1
+# Command line: vivado.exe -log esdi_ctl_phy.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace
+# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy.vdi
+# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source esdi_ctl_phy.tcl -notrace
+Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7z007sclg225-1
+INFO: [Project 1-479] Netlist was created with Vivado 2019.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               0  |                                              0  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              0  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
+Ending Logic Optimization Task | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
+Ending Netlist Obfuscation Task | Checksum: 686e1c75
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx
+Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 2 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000
+Phase 1 Placer Initialization | Checksum: 00000000
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000
+ERROR: [Place 30-494] The design is empty
+Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.
+Ending Placer Task | Checksum: 00000000
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000
+INFO: [Common 17-83] Releasing license: Implementation
+37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.
+place_design failed
+ERROR: [Common 17-69] Command failed: Placer could not place all instances
+INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019...

diff --git a/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb
new file mode 100644 (file)
index 0000000..70698d1
Binary files /dev/null and b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.pb differ

diff --git a/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt
new file mode 100644 (file)
index 0000000..e642738
--- /dev/null
+++ b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt
@@ -0,0 +1,41 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
+| Date         : Tue Aug 13 10:39:56 2019
+| Host         : KREMLINMACHINE running 64-bit major release  (build 9200)
+| Command      : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx
+| Design       : esdi_ctl_phy
+| Device       : xc7z007sclg225-1
+| Speed File   : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 1
++--------+----------+--------------------+------------+
+| Rule   | Severity | Description        | Violations |
++--------+----------+--------------------+------------+
+| ZPS7-1 | Warning  | PS7 block required | 1          |
++--------+----------+--------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+ZPS7-1#1 Warning
+PS7 block required  
+The PS7 cell must be used in this Zynq design in order to enable correct default configuration.
+Related violations: <none>
+
+

diff --git a/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpx b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpx
new file mode 100644 (file)
index 0000000..7dda7ab
Binary files /dev/null and b/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpx differ

diff --git a/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp b/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp
new file mode 100644 (file)
index 0000000..b282a6a
Binary files /dev/null and b/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp differ

diff --git a/esdi.runs/impl_1/gen_run.xml b/esdi.runs/impl_1/gen_run.xml
new file mode 100644 (file)
index 0000000..80fb6ef
--- /dev/null
+++ b/esdi.runs/impl_1/gen_run.xml
@@ -0,0 +1,121 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<GenRun Id="impl_1" LaunchPart="xc7z007sclg225-1" LaunchTime="1565710761">\r
+  <File Type="BITSTR-BMM" Name="esdi_ctl_phy_bd.bmm"/>\r
+  <File Type="OPT-METHODOLOGY-DRC" Name="esdi_ctl_phy_methodology_drc_opted.rpt"/>\r
+  <File Type="INIT-TIMING" Name="esdi_ctl_phy_timing_summary_init.rpt"/>\r
+  <File Type="ROUTE-PWR" Name="esdi_ctl_phy_power_routed.rpt"/>\r
+  <File Type="PA-TCL" Name="esdi_ctl_phy.tcl"/>\r
+  <File Type="OPT-TIMING" Name="esdi_ctl_phy_timing_summary_opted.rpt"/>\r
+  <File Type="OPT-DCP" Name="esdi_ctl_phy_opt.dcp"/>\r
+  <File Type="ROUTE-PWR-SUM" Name="esdi_ctl_phy_power_summary_routed.pb"/>\r
+  <File Type="REPORTS-TCL" Name="esdi_ctl_phy_reports.tcl"/>\r
+  <File Type="OPT-DRC" Name="esdi_ctl_phy_drc_opted.rpt"/>\r
+  <File Type="OPT-HWDEF" Name="esdi_ctl_phy.hwdef"/>\r
+  <File Type="PWROPT-DCP" Name="esdi_ctl_phy_pwropt.dcp"/>\r
+  <File Type="PWROPT-DRC" Name="esdi_ctl_phy_drc_pwropted.rpt"/>\r
+  <File Type="PWROPT-TIMING" Name="esdi_ctl_phy_timing_summary_pwropted.rpt"/>\r
+  <File Type="PLACE-DCP" Name="esdi_ctl_phy_placed.dcp"/>\r
+  <File Type="PLACE-IO" Name="esdi_ctl_phy_io_placed.rpt"/>\r
+  <File Type="PLACE-CLK" Name="esdi_ctl_phy_clock_utilization_placed.rpt"/>\r
+  <File Type="PLACE-UTIL" Name="esdi_ctl_phy_utilization_placed.rpt"/>\r
+  <File Type="PLACE-UTIL-PB" Name="esdi_ctl_phy_utilization_placed.pb"/>\r
+  <File Type="PLACE-CTRL" Name="esdi_ctl_phy_control_sets_placed.rpt"/>\r
+  <File Type="PLACE-SIMILARITY" Name="esdi_ctl_phy_incremental_reuse_placed.rpt"/>\r
+  <File Type="PLACE-PRE-SIMILARITY" Name="esdi_ctl_phy_incremental_reuse_pre_placed.rpt"/>\r
+  <File Type="BG-BGN" Name="esdi_ctl_phy.bgn"/>\r
+  <File Type="PLACE-TIMING" Name="esdi_ctl_phy_timing_summary_placed.rpt"/>\r
+  <File Type="POSTPLACE-PWROPT-DCP" Name="esdi_ctl_phy_postplace_pwropt.dcp"/>\r
+  <File Type="BG-BIN" Name="esdi_ctl_phy.bin"/>\r
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="esdi_ctl_phy_timing_summary_postplace_pwropted.rpt"/>\r
+  <File Type="PHYSOPT-DCP" Name="esdi_ctl_phy_physopt.dcp"/>\r
+  <File Type="PHYSOPT-DRC" Name="esdi_ctl_phy_drc_physopted.rpt"/>\r
+  <File Type="BITSTR-MSK" Name="esdi_ctl_phy.msk"/>\r
+  <File Type="PHYSOPT-TIMING" Name="esdi_ctl_phy_timing_summary_physopted.rpt"/>\r
+  <File Type="ROUTE-ERROR-DCP" Name="esdi_ctl_phy_routed_error.dcp"/>\r
+  <File Type="ROUTE-DCP" Name="esdi_ctl_phy_routed.dcp"/>\r
+  <File Type="ROUTE-BLACKBOX-DCP" Name="esdi_ctl_phy_routed_bb.dcp"/>\r
+  <File Type="ROUTE-DRC" Name="esdi_ctl_phy_drc_routed.rpt"/>\r
+  <File Type="ROUTE-DRC-PB" Name="esdi_ctl_phy_drc_routed.pb"/>\r
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>\r
+  <File Type="BITSTR-LTX" Name="esdi_ctl_phy.ltx"/>\r
+  <File Type="ROUTE-DRC-RPX" Name="esdi_ctl_phy_drc_routed.rpx"/>\r
+  <File Type="BITSTR-MMI" Name="esdi_ctl_phy.mmi"/>\r
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="esdi_ctl_phy_methodology_drc_routed.rpt"/>\r
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="esdi_ctl_phy_methodology_drc_routed.rpx"/>\r
+  <File Type="BITSTR-SYSDEF" Name="esdi_ctl_phy.sysdef"/>\r
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="esdi_ctl_phy_methodology_drc_routed.pb"/>\r
+  <File Type="ROUTE-PWR-RPX" Name="esdi_ctl_phy_power_routed.rpx"/>\r
+  <File Type="ROUTE-STATUS" Name="esdi_ctl_phy_route_status.rpt"/>\r
+  <File Type="ROUTE-STATUS-PB" Name="esdi_ctl_phy_route_status.pb"/>\r
+  <File Type="ROUTE-TIMINGSUMMARY" Name="esdi_ctl_phy_timing_summary_routed.rpt"/>\r
+  <File Type="ROUTE-TIMING-PB" Name="esdi_ctl_phy_timing_summary_routed.pb"/>\r
+  <File Type="ROUTE-TIMING-RPX" Name="esdi_ctl_phy_timing_summary_routed.rpx"/>\r
+  <File Type="ROUTE-SIMILARITY" Name="esdi_ctl_phy_incremental_reuse_routed.rpt"/>\r
+  <File Type="ROUTE-CLK" Name="esdi_ctl_phy_clock_utilization_routed.rpt"/>\r
+  <File Type="ROUTE-BUS-SKEW" Name="esdi_ctl_phy_bus_skew_routed.rpt"/>\r
+  <File Type="ROUTE-BUS-SKEW-PB" Name="esdi_ctl_phy_bus_skew_routed.pb"/>\r
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="esdi_ctl_phy_bus_skew_routed.rpx"/>\r
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="esdi_ctl_phy_postroute_physopt.dcp"/>\r
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="esdi_ctl_phy_postroute_physopt_bb.dcp"/>\r
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="esdi_ctl_phy_timing_summary_postroute_physopted.rpt"/>\r
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="esdi_ctl_phy_timing_summary_postroute_physopted.pb"/>\r
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="esdi_ctl_phy_timing_summary_postroute_physopted.rpx"/>\r
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="esdi_ctl_phy_bus_skew_postroute_physopted.rpt"/>\r
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="esdi_ctl_phy_bus_skew_postroute_physopted.pb"/>\r
+  <File Type="BG-BIT" Name="esdi_ctl_phy.bit"/>\r
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="esdi_ctl_phy_bus_skew_postroute_physopted.rpx"/>\r
+  <File Type="BITSTR-RBT" Name="esdi_ctl_phy.rbt"/>\r
+  <File Type="BITSTR-NKY" Name="esdi_ctl_phy.nky"/>\r
+  <File Type="BG-DRC" Name="esdi_ctl_phy.drc"/>\r
+  <File Type="RDI-RDI" Name="esdi_ctl_phy.vdi"/>\r
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>\r
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">\r
+    <Filter Type="Srcs"/>\r
+    <File Path="$PSRCDIR/sources_1/new/esdi_phy_ctl.v">\r
+      <FileInfo>\r
+        <Attr Name="UsedIn" Val="synthesis"/>\r
+        <Attr Name="UsedIn" Val="implementation"/>\r
+        <Attr Name="UsedIn" Val="simulation"/>\r
+      </FileInfo>\r
+    </File>\r
+    <File Path="$PSRCDIR/sources_1/new/esdi_data_phy.v">\r
+      <FileInfo>\r
+        <Attr Name="AutoDisabled" Val="1"/>\r
+        <Attr Name="UsedIn" Val="synthesis"/>\r
+        <Attr Name="UsedIn" Val="implementation"/>\r
+        <Attr Name="UsedIn" Val="simulation"/>\r
+      </FileInfo>\r
+    </File>\r
+    <Config>\r
+      <Option Name="DesignMode" Val="RTL"/>\r
+      <Option Name="TopModule" Val="esdi_ctl_phy"/>\r
+      <Option Name="TopAutoSet" Val="TRUE"/>\r
+    </Config>\r
+  </FileSet>\r
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">\r
+    <Filter Type="Constrs"/>\r
+    <Config>\r
+      <Option Name="ConstrsType" Val="XDC"/>\r
+    </Config>\r
+  </FileSet>\r
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">\r
+    <Filter Type="Utils"/>\r
+    <Config>\r
+      <Option Name="TopAutoSet" Val="TRUE"/>\r
+    </Config>\r
+  </FileSet>\r
+  <Strategy Version="1" Minor="2">\r
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">\r
+      <Desc>Default settings for Implementation.</Desc>\r
+    </StratHandle>\r
+    <Step Id="init_design"/>\r
+    <Step Id="opt_design"/>\r
+    <Step Id="power_opt_design"/>\r
+    <Step Id="place_design"/>\r
+    <Step Id="post_place_power_opt_design"/>\r
+    <Step Id="phys_opt_design"/>\r
+    <Step Id="route_design"/>\r
+    <Step Id="post_route_phys_opt_design"/>\r
+    <Step Id="write_bitstream"/>\r
+  </Strategy>\r
+</GenRun>\r

diff --git a/esdi.runs/impl_1/htr.txt b/esdi.runs/impl_1/htr.txt
new file mode 100644 (file)
index 0000000..2aa84a6
--- /dev/null
+++ b/esdi.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+REM\r
+REM Vivado(TM)\r
+REM htr.txt: a Vivado-generated description of how-to-repeat the\r
+REM          the basic steps of a run.  Note that runme.bat/sh needs\r
+REM          to be invoked for Vivado to track run status.\r
+REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+REM\r
+\r
+vivado -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace\r

diff --git a/esdi.runs/impl_1/init_design.pb b/esdi.runs/impl_1/init_design.pb
new file mode 100644 (file)
index 0000000..839a9b4
Binary files /dev/null and b/esdi.runs/impl_1/init_design.pb differ

diff --git a/esdi.runs/impl_1/opt_design.pb b/esdi.runs/impl_1/opt_design.pb
new file mode 100644 (file)
index 0000000..5ee97af
Binary files /dev/null and b/esdi.runs/impl_1/opt_design.pb differ

diff --git a/esdi.runs/impl_1/place_design.pb b/esdi.runs/impl_1/place_design.pb
new file mode 100644 (file)
index 0000000..44dfd10
Binary files /dev/null and b/esdi.runs/impl_1/place_design.pb differ

diff --git a/esdi.runs/impl_1/project.wdf b/esdi.runs/impl_1/project.wdf
new file mode 100644 (file)
index 0000000..a54295a
--- /dev/null
+++ b/esdi.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@
+version:1\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00\r
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00\r
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3766626462656662353231383438653961626661396637663131336536353232:506172656e742050412070726f6a656374204944:00\r
+eof:3165293120\r

diff --git a/esdi.runs/impl_1/rundef.js b/esdi.runs/impl_1/rundef.js
new file mode 100644 (file)
index 0000000..e169657
--- /dev/null
+++ b/esdi.runs/impl_1/rundef.js
@@ -0,0 +1,40 @@
+//\r
+// Vivado(TM)\r
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6\r
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+//\r
+\r
+var WshShell = new ActiveXObject( "WScript.Shell" );\r
+var ProcEnv = WshShell.Environment( "Process" );\r
+var PathVal = ProcEnv("PATH");\r
+if ( PathVal.length == 0 ) {\r
+  PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;";\r
+} else {\r
+  PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;" + PathVal;\r
+}\r
+\r
+ProcEnv("PATH") = PathVal;\r
+\r
+var RDScrFP = WScript.ScriptFullName;\r
+var RDScrN = WScript.ScriptName;\r
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );\r
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";\r
+eval( EAInclude(ISEJScriptLib) );\r
+\r
+\r
+// pre-commands:\r
+ISETouchFile( "init_design", "begin" );\r
+ISEStep( "vivado",\r
+         "-log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace" );\r
+\r
+\r
+\r
+\r
+\r
+function EAInclude( EAInclFilename ) {\r
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );\r
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );\r
+  var EAIFContents = EAInclFile.ReadAll();\r
+  EAInclFile.Close();\r
+  return EAIFContents;\r
+}\r

diff --git a/esdi.runs/impl_1/runme.bat b/esdi.runs/impl_1/runme.bat
new file mode 100644 (file)
index 0000000..bc78723
--- /dev/null
+++ b/esdi.runs/impl_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off\r
+\r
+rem  Vivado (TM)\r
+rem  runme.bat: a Vivado-generated Script\r
+rem  Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+\r
+\r
+set HD_SDIR=%~dp0\r
+cd /d "%HD_SDIR%"\r
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*\r

diff --git a/esdi.runs/impl_1/runme.log b/esdi.runs/impl_1/runme.log
new file mode 100644 (file)
index 0000000..15952e6
--- /dev/null
+++ b/esdi.runs/impl_1/runme.log
@@ -0,0 +1,173 @@
+\r
+*** Running vivado\r
+    with args -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace\r
+\r
+\r
+****** Vivado v2019.1 (64-bit)\r
+  **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019\r
+  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019\r
+    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+\r
+source esdi_ctl_phy.tcl -notrace\r
+Command: link_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
+Design is defaulting to srcset: sources_1\r
+Design is defaulting to constrset: constrs_1\r
+INFO: [Device 21-403] Loading part xc7z007sclg225-1\r
+INFO: [Project 1-479] Netlist was created with Vivado 2019.1\r
+INFO: [Project 1-570] Preparing netlist for logic optimization\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 746.855 ; gain = 0.000\r
+INFO: [Project 1-111] Unisim Transformation Summary:\r
+No Unisim elements were transformed.\r
+\r
+4 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
+link_design completed successfully\r
+link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 746.855 ; gain = 348.582\r
+Command: opt_design\r
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r
+Running DRC as a precondition to command opt_design\r
+\r
+Starting DRC Task\r
+INFO: [DRC 23-27] Running DRC with 2 threads\r
+INFO: [Project 1-461] DRC finished with 0 Errors\r
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.\r
+\r
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.089 . Memory (MB): peak = 772.863 ; gain = 25.824\r
+\r
+Starting Cache Timing Information Task\r
+INFO: [Timing 38-35] Done setting XDC timing constraints.\r
+Ending Cache Timing Information Task | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1245.227 ; gain = 472.363\r
+\r
+Starting Logic Optimization Task\r
+\r
+Phase 1 Retarget\r
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
+INFO: [Opt 31-49] Retargeted 0 cell(s).\r
+Phase 1 Retarget | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells\r
+\r
+Phase 2 Constant propagation\r
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
+Phase 2 Constant propagation | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells\r
+\r
+Phase 3 Sweep\r
+Phase 3 Sweep | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.035 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells\r
+\r
+Phase 4 BUFG optimization\r
+Phase 4 BUFG optimization | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.037 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.\r
+\r
+Phase 5 Shift Register Optimization\r
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs\r
+Phase 5 Shift Register Optimization | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells\r
+\r
+Phase 6 Post Processing Netlist\r
+Phase 6 Post Processing Netlist | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.040 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells\r
+Opt_design Change Summary\r
+=========================\r
+\r
+\r
+-------------------------------------------------------------------------------------------------------------------------\r
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |\r
+-------------------------------------------------------------------------------------------------------------------------\r
+|  Retarget                     |               0  |               0  |                                              0  |\r
+|  Constant propagation         |               0  |               0  |                                              0  |\r
+|  Sweep                        |               0  |               0  |                                              0  |\r
+|  BUFG optimization            |               0  |               0  |                                              0  |\r
+|  Shift Register Optimization  |               0  |               0  |                                              0  |\r
+|  Post Processing Netlist      |               0  |               0  |                                              0  |\r
+-------------------------------------------------------------------------------------------------------------------------\r
+\r
+\r
+\r
+Starting Connectivity Check Task\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+Ending Logic Optimization Task | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 1400.414 ; gain = 14.781\r
+\r
+Starting Power Optimization Task\r
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.\r
+Ending Power Optimization Task | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+\r
+Starting Final Cleanup Task\r
+Ending Final Cleanup Task | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+\r
+Starting Netlist Obfuscation Task\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+Ending Netlist Obfuscation Task | Checksum: 686e1c75\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+INFO: [Common 17-83] Releasing license: Implementation\r
+21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
+opt_design completed successfully\r
+opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1400.414 ; gain = 653.559\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1400.414 ; gain = 0.000\r
+WARNING: [Constraints 18-5210] No constraints selected for write.\r
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.\r
+INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_opt.dcp' has been generated.\r
+INFO: [runtcl-4] Executing : report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r
+Command: report_drc -file esdi_ctl_phy_drc_opted.rpt -pb esdi_ctl_phy_drc_opted.pb -rpx esdi_ctl_phy_drc_opted.rpx\r
+INFO: [IP_Flow 19-234] Refreshing IP repositories\r
+INFO: [IP_Flow 19-1704] No user IP repositories specified\r
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'S:/vivado/Vivado/2019.1/data/ip'.\r
+INFO: [DRC 23-27] Running DRC with 2 threads\r
+INFO: [Coretcl 2-168] The results of DRC are in file S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy_drc_opted.rpt.\r
+report_drc completed successfully\r
+Command: place_design\r
+Attempting to get a license for feature 'Implementation' and/or device 'xc7z007s'\r
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z007s'\r
+INFO: [DRC 23-27] Running DRC with 2 threads\r
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r
+Running DRC as a precondition to command place_design\r
+INFO: [DRC 23-27] Running DRC with 2 threads\r
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors\r
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.\r
+\r
+Starting Placer Task\r
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs\r
+\r
+Phase 1 Placer Initialization\r
+\r
+Phase 1.1 Placer Initialization Netlist Sorting\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 00000000\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
+Phase 1 Placer Initialization | Checksum: 00000000\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
+ERROR: [Place 30-494] The design is empty\r
+Resolution: Check if opt_design has removed all the leaf cells of your design.  Check whether you have instantiated and connected all of the top level ports.\r
+Ending Placer Task | Checksum: 00000000\r
+\r
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 1420.277 ; gain = 0.000\r
+INFO: [Common 17-83] Releasing license: Implementation\r
+37 Infos, 1 Warnings, 0 Critical Warnings and 2 Errors encountered.\r
+place_design failed\r
+ERROR: [Common 17-69] Command failed: Placer could not place all instances\r
+INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:56 2019...\r

diff --git a/esdi.runs/impl_1/runme.sh b/esdi.runs/impl_1/runme.sh
new file mode 100644 (file)
index 0000000..6a4a4d5
--- /dev/null
+++ b/esdi.runs/impl_1/runme.sh
@@ -0,0 +1,47 @@
+#!/bin/sh\r
+\r
+# \r
+# Vivado(TM)\r
+# runme.sh: a Vivado-generated Runs Script for UNIX\r
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+# \r
+\r
+echo "This script was generated under a different operating system."\r
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"\r
+exit\r
+\r
+if [ -z "$PATH" ]; then\r
+  PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin\r
+else\r
+  PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin:$PATH\r
+fi\r
+export PATH\r
+\r
+if [ -z "$LD_LIBRARY_PATH" ]; then\r
+  LD_LIBRARY_PATH=\r
+else\r
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH\r
+fi\r
+export LD_LIBRARY_PATH\r
+\r
+HD_PWD='S:/vivado-projects/esdi/esdi/esdi.runs/impl_1'\r
+cd "$HD_PWD"\r
+\r
+HD_LOG=runme.log\r
+/bin/touch $HD_LOG\r
+\r
+ISEStep="./ISEWrap.sh"\r
+EAStep()\r
+{\r
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1\r
+     if [ $? -ne 0 ]\r
+     then\r
+         exit\r
+     fi\r
+}\r
+\r
+# pre-commands:\r
+/bin/touch .init_design.begin.rst\r
+EAStep vivado -log esdi_ctl_phy.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace\r
+\r
+\r

diff --git a/esdi.runs/impl_1/vivado.jou b/esdi.runs/impl_1/vivado.jou
new file mode 100644 (file)
index 0000000..ff9b6ad
--- /dev/null
+++ b/esdi.runs/impl_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2019.1 (64-bit)
+# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
+# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
+# Start of session at: Tue Aug 13 10:39:28 2019
+# Process ID: 13936
+# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1
+# Command line: vivado.exe -log esdi_ctl_phy.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source esdi_ctl_phy.tcl -notrace
+# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1/esdi_ctl_phy.vdi
+# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/impl_1\vivado.jou
+#-----------------------------------------------------------
+source esdi_ctl_phy.tcl -notrace

diff --git a/esdi.runs/impl_1/vivado.pb b/esdi.runs/impl_1/vivado.pb
new file mode 100644 (file)
index 0000000..b155e40
--- /dev/null
+++ b/esdi.runs/impl_1/vivado.pb
@@ -0,0 +1,4 @@
+
+\ e
+
+End Record\10\ 1
\ No newline at end of file

diff --git a/esdi.runs/synth_1/.Vivado_Synthesis.queue.rst b/esdi.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/synth_1/.vivado.begin.rst b/esdi.runs/synth_1/.vivado.begin.rst
new file mode 100644 (file)
index 0000000..c39ccbb
--- /dev/null
+++ b/esdi.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>\r
+<ProcessHandle Version="1" Minor="0">\r
+    <Process Command="vivado.bat" Owner="kremlin" Host="KREMLINMACHINE" Pid="18212" HostCore="24" HostMemory="034235731968">\r
+    </Process>\r
+</ProcessHandle>\r

diff --git a/esdi.runs/synth_1/.vivado.end.rst b/esdi.runs/synth_1/.vivado.end.rst
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/synth_1/ISEWrap.js b/esdi.runs/synth_1/ISEWrap.js
new file mode 100644 (file)
index 0000000..3e83de1
--- /dev/null
+++ b/esdi.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+              ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+                           "\" Owner=\"" + ISEUser + 
+                           "\" Host=\"" + ISEHost + 
+                           "\" Pid=\"" + ISEPid +
+                           "\" HostCore=\"" + ISEHOSTCORE +
+                           "\" HostMemory=\"" + ISEMEMTOTAL +
+                           "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {\r
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);\r
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}

diff --git a/esdi.runs/synth_1/ISEWrap.sh b/esdi.runs/synth_1/ISEWrap.sh
new file mode 100644 (file)
index 0000000..f679f2e
--- /dev/null
+++ b/esdi.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,67 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. 
+#
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+if [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+

diff --git a/esdi.runs/synth_1/__synthesis_is_complete__ b/esdi.runs/synth_1/__synthesis_is_complete__
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/esdi.runs/synth_1/esdi_ctl_phy.dcp b/esdi.runs/synth_1/esdi_ctl_phy.dcp
new file mode 100644 (file)
index 0000000..b783168
Binary files /dev/null and b/esdi.runs/synth_1/esdi_ctl_phy.dcp differ

diff --git a/esdi.runs/synth_1/esdi_ctl_phy.tcl b/esdi.runs/synth_1/esdi_ctl_phy.tcl
new file mode 100644 (file)
index 0000000..d9a824d
--- /dev/null
+++ b/esdi.runs/synth_1/esdi_ctl_phy.tcl
@@ -0,0 +1,53 @@
+# \r
+# Synthesis run script generated by Vivado\r
+# \r
+\r
+set TIME_start [clock seconds] \r
+proc create_report { reportName command } {\r
+  set status "."\r
+  append status $reportName ".fail"\r
+  if { [file exists $status] } {\r
+    eval file delete [glob $status]\r
+  }\r
+  send_msg_id runtcl-4 info "Executing : $command"\r
+  set retval [eval catch { $command } msg]\r
+  if { $retval != 0 } {\r
+    set fp [open $status w]\r
+    close $fp\r
+    send_msg_id runtcl-5 warning "$msg"\r
+  }\r
+}\r
+create_project -in_memory -part xc7z007sclg225-1\r
+\r
+set_param project.singleFileAddWarning.threshold 0\r
+set_param project.compositeFile.enableAutoGeneration 0\r
+set_param synth.vivado.isSynthRun true\r
+set_property webtalk.parent_dir S:/vivado-projects/esdi/esdi/esdi.cache/wt [current_project]\r
+set_property parent.project_path S:/vivado-projects/esdi/esdi/esdi.xpr [current_project]\r
+set_property default_lib xil_defaultlib [current_project]\r
+set_property target_language Verilog [current_project]\r
+set_property board_part_repo_paths {C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store} [current_project]\r
+set_property board_part em.avnet.com:minized:part0:1.2 [current_project]\r
+set_property ip_output_repo s:/vivado-projects/esdi/esdi/esdi.cache/ip [current_project]\r
+set_property ip_cache_permissions {read write} [current_project]\r
+read_verilog -library xil_defaultlib S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v\r
+# Mark all dcp files as not used in implementation to prevent them from being\r
+# stitched into the results of this synthesis run. Any black boxes in the\r
+# design are intentionally left as such for best results. Dcp files will be\r
+# stitched into the design at a later time, either when this synthesis run is\r
+# opened, or when it is stitched into a dependent implementation run.\r
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {\r
+  set_property used_in_implementation false $dcp\r
+}\r
+set_param ips.enableIPCacheLiteLoad 1\r
+close [open __synthesis_is_running__ w]\r
+\r
+synth_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
+\r
+\r
+# disable binary constraint mode for synth run checkpoints\r
+set_param constraints.enableBinaryConstraints false\r
+write_checkpoint -force -noxdef esdi_ctl_phy.dcp\r
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb"\r
+file delete __synthesis_is_running__\r
+close [open __synthesis_is_complete__ w]\r

diff --git a/esdi.runs/synth_1/esdi_ctl_phy.vds b/esdi.runs/synth_1/esdi_ctl_phy.vds
new file mode 100644 (file)
index 0000000..4dc8027
--- /dev/null
+++ b/esdi.runs/synth_1/esdi_ctl_phy.vds
@@ -0,0 +1,218 @@
+#-----------------------------------------------------------
+# Vivado v2019.1 (64-bit)
+# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
+# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
+# Start of session at: Tue Aug 13 10:38:50 2019
+# Process ID: 20424
+# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1
+# Command line: vivado.exe -log esdi_ctl_phy.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl
+# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.vds
+# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source esdi_ctl_phy.tcl -notrace
+Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s'
+INFO: Launching helper process for spawning children vivado processes
+INFO: Helper process launched with PID 18332 
+---------------------------------------------------------------------------------
+Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
+INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]
+WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
+---------------------------------------------------------------------------------
+Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7z007sclg225-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852
+---------------------------------------------------------------------------------
+INFO: [Device 21-403] Loading part xc7z007sclg225-1
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+No constraint files found.
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Hierarchical Component Statistics 
+---------------------------------------------------------------------------------
+Hierarchical RTL Component report 
+---------------------------------------------------------------------------------
+Finished RTL Hierarchical Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 66 (col length:40)
+BRAMs: 100 (col length: RAMB18 40 RAMB36 20)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+Warning: Parallel synthesis criteria is not met 
+WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+No constraint files found.
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+
+Report Check Netlist: 
++------+------------------+-------+---------+-------+------------------+
+|      |Item              |Errors |Warnings |Status |Description       |
++------+------------------+-------+---------+-------+------------------+
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
++------+------------------+-------+---------+-------+------------------+
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+
+Report RTL Partitions: 
++-+--------------+------------+----------+
+| |RTL Partition |Replication |Instances |
++-+--------------+------------+----------+
++-+--------------+------------+----------+
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+-------------+------+
+|      |Cell         |Count |
++------+-------------+------+
+|1     |esdi_ctl_phy |     1|
++------+-------------+------+
+
+Report Instance Areas: 
++------+---------+-------+------+
+|      |Instance |Module |Cells |
++------+---------+-------+------+
+|1     |top      |       |     0|
++------+---------+-------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211
+INFO: [Project 1-571] Translating synthesized netlist
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+INFO: [Common 17-83] Releasing license: Synthesis
+9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000
+WARNING: [Constraints 18-5210] No constraints selected for write.
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.
+INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019...

diff --git a/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb
new file mode 100644 (file)
index 0000000..8926a67
Binary files /dev/null and b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.pb differ

diff --git a/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt
new file mode 100644 (file)
index 0000000..3323731
--- /dev/null
+++ b/esdi.runs/synth_1/esdi_ctl_phy_utilization_synth.rpt
@@ -0,0 +1,187 @@
+Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
+| Date         : Tue Aug 13 10:39:11 2019
+| Host         : KREMLINMACHINE running 64-bit major release  (build 9200)
+| Command      : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb
+| Design       : esdi_ctl_phy
+| Device       : 7z007sclg225-1
+| Design State : Fully Placed
+-------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+-----------+-------+
+|        Site Type        | Used | Fixed | Available | Util% |
++-------------------------+------+-------+-----------+-------+
+| Slice LUTs              |    0 |     0 |     14400 |  0.00 |
+|   LUT as Logic          |    0 |     0 |     14400 |  0.00 |
+|   LUT as Memory         |    0 |     0 |      6000 |  0.00 |
+| Slice Registers         |    0 |     0 |     28800 |  0.00 |
+|   Register as Flip Flop |    0 |     0 |     28800 |  0.00 |
+|   Register as Latch     |    0 |     0 |     28800 |  0.00 |
+| F7 Muxes                |    0 |     0 |      8800 |  0.00 |
+| F8 Muxes                |    0 |     0 |      4400 |  0.00 |
++-------------------------+------+-------+-----------+-------+
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 0     |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 0     |          Yes |         Set |            - |
+| 0     |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++------------------------------------------+------+-------+-----------+-------+
+|                 Site Type                | Used | Fixed | Available | Util% |
++------------------------------------------+------+-------+-----------+-------+
+| Slice                                    |    0 |     0 |      4400 |  0.00 |
+|   SLICEL                                 |    0 |     0 |           |       |
+|   SLICEM                                 |    0 |     0 |           |       |
+| LUT as Logic                             |    0 |     0 |     14400 |  0.00 |
+| LUT as Memory                            |    0 |     0 |      6000 |  0.00 |
+|   LUT as Distributed RAM                 |    0 |     0 |           |       |
+|   LUT as Shift Register                  |    0 |     0 |           |       |
+| Slice Registers                          |    0 |     0 |     28800 |  0.00 |
+|   Register driven from within the Slice  |    0 |       |           |       |
+|   Register driven from outside the Slice |    0 |       |           |       |
+| Unique Control Sets                      |    0 |       |      4400 |  0.00 |
++------------------------------------------+------+-------+-----------+-------+
+* Note: Available Control Sets calculated as Slice Registers / 8, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+-----------+-------+
+|    Site Type   | Used | Fixed | Available | Util% |
++----------------+------+-------+-----------+-------+
+| Block RAM Tile |    0 |     0 |        50 |  0.00 |
+|   RAMB36/FIFO* |    0 |     0 |        50 |  0.00 |
+|   RAMB18       |    0 |     0 |       100 |  0.00 |
++----------------+------+-------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+-----------+-------+
+| Site Type | Used | Fixed | Available | Util% |
++-----------+------+-------+-----------+-------+
+| DSPs      |    0 |     0 |        66 |  0.00 |
++-----------+------+-------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+-----------+-------+
+|          Site Type          | Used | Fixed | Available | Util% |
++-----------------------------+------+-------+-----------+-------+
+| Bonded IOB                  |    0 |     0 |        54 |  0.00 |
+| Bonded IPADs                |    0 |     0 |         2 |  0.00 |
+| Bonded IOPADs               |    0 |     0 |       130 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |         2 |  0.00 |
+| PHASER_REF                  |    0 |     0 |         2 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |         8 |  0.00 |
+| IN_FIFO                     |    0 |     0 |         8 |  0.00 |
+| IDELAYCTRL                  |    0 |     0 |         2 |  0.00 |
+| IBUFDS                      |    0 |     0 |        54 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |         8 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |         8 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    0 |     0 |       100 |  0.00 |
+| ILOGIC                      |    0 |     0 |        54 |  0.00 |
+| OLOGIC                      |    0 |     0 |        54 |  0.00 |
++-----------------------------+------+-------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+-----------+-------+
+|  Site Type | Used | Fixed | Available | Util% |
++------------+------+-------+-----------+-------+
+| BUFGCTRL   |    0 |     0 |        32 |  0.00 |
+| BUFIO      |    0 |     0 |         8 |  0.00 |
+| MMCME2_ADV |    0 |     0 |         2 |  0.00 |
+| PLLE2_ADV  |    0 |     0 |         2 |  0.00 |
+| BUFMRCE    |    0 |     0 |         4 |  0.00 |
+| BUFHCE     |    0 |     0 |        48 |  0.00 |
+| BUFR       |    0 |     0 |         8 |  0.00 |
++------------+------+-------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+-----------+-------+
+|  Site Type  | Used | Fixed | Available | Util% |
++-------------+------+-------+-----------+-------+
+| BSCANE2     |    0 |     0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |         2 |  0.00 |
+| STARTUPE2   |    0 |     0 |         1 |  0.00 |
+| XADC        |    0 |     0 |         1 |  0.00 |
++-------------+------+-------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+

diff --git a/esdi.runs/synth_1/gen_run.xml b/esdi.runs/synth_1/gen_run.xml
new file mode 100644 (file)
index 0000000..9848585
--- /dev/null
+++ b/esdi.runs/synth_1/gen_run.xml
@@ -0,0 +1,53 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<GenRun Id="synth_1" LaunchPart="xc7z007sclg225-1" LaunchTime="1565710727">\r
+  <File Type="PA-TCL" Name="esdi_ctl_phy.tcl"/>\r
+  <File Type="RDS-PROPCONSTRS" Name="esdi_ctl_phy_drc_synth.rpt"/>\r
+  <File Type="REPORTS-TCL" Name="esdi_ctl_phy_reports.tcl"/>\r
+  <File Type="RDS-RDS" Name="esdi_ctl_phy.vds"/>\r
+  <File Type="RDS-UTIL" Name="esdi_ctl_phy_utilization_synth.rpt"/>\r
+  <File Type="RDS-UTIL-PB" Name="esdi_ctl_phy_utilization_synth.pb"/>\r
+  <File Type="RDS-DCP" Name="esdi_ctl_phy.dcp"/>\r
+  <File Type="VDS-TIMINGSUMMARY" Name="esdi_ctl_phy_timing_summary_synth.rpt"/>\r
+  <File Type="VDS-TIMING-PB" Name="esdi_ctl_phy_timing_summary_synth.pb"/>\r
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">\r
+    <Filter Type="Srcs"/>\r
+    <File Path="$PSRCDIR/sources_1/new/esdi_phy_ctl.v">\r
+      <FileInfo>\r
+        <Attr Name="UsedIn" Val="synthesis"/>\r
+        <Attr Name="UsedIn" Val="implementation"/>\r
+        <Attr Name="UsedIn" Val="simulation"/>\r
+      </FileInfo>\r
+    </File>\r
+    <File Path="$PSRCDIR/sources_1/new/esdi_data_phy.v">\r
+      <FileInfo>\r
+        <Attr Name="AutoDisabled" Val="1"/>\r
+        <Attr Name="UsedIn" Val="synthesis"/>\r
+        <Attr Name="UsedIn" Val="implementation"/>\r
+        <Attr Name="UsedIn" Val="simulation"/>\r
+      </FileInfo>\r
+    </File>\r
+    <Config>\r
+      <Option Name="DesignMode" Val="RTL"/>\r
+      <Option Name="TopModule" Val="esdi_ctl_phy"/>\r
+      <Option Name="TopAutoSet" Val="TRUE"/>\r
+    </Config>\r
+  </FileSet>\r
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">\r
+    <Filter Type="Constrs"/>\r
+    <Config>\r
+      <Option Name="ConstrsType" Val="XDC"/>\r
+    </Config>\r
+  </FileSet>\r
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">\r
+    <Filter Type="Utils"/>\r
+    <Config>\r
+      <Option Name="TopAutoSet" Val="TRUE"/>\r
+    </Config>\r
+  </FileSet>\r
+  <Strategy Version="1" Minor="2">\r
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">\r
+      <Desc>Vivado Synthesis Defaults</Desc>\r
+    </StratHandle>\r
+    <Step Id="synth_design"/>\r
+  </Strategy>\r
+</GenRun>\r

diff --git a/esdi.runs/synth_1/htr.txt b/esdi.runs/synth_1/htr.txt
new file mode 100644 (file)
index 0000000..22342a3
--- /dev/null
+++ b/esdi.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+REM\r
+REM Vivado(TM)\r
+REM htr.txt: a Vivado-generated description of how-to-repeat the\r
+REM          the basic steps of a run.  Note that runme.bat/sh needs\r
+REM          to be invoked for Vivado to track run status.\r
+REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+REM\r
+\r
+vivado -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl\r

diff --git a/esdi.runs/synth_1/project.wdf b/esdi.runs/synth_1/project.wdf
new file mode 100644 (file)
index 0000000..a54295a
--- /dev/null
+++ b/esdi.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:41637469766548444c:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00\r
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00\r
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3766626462656662353231383438653961626661396637663131336536353232:506172656e742050412070726f6a656374204944:00\r
+eof:3165293120\r

diff --git a/esdi.runs/synth_1/rundef.js b/esdi.runs/synth_1/rundef.js
new file mode 100644 (file)
index 0000000..f3457d8
--- /dev/null
+++ b/esdi.runs/synth_1/rundef.js
@@ -0,0 +1,36 @@
+//\r
+// Vivado(TM)\r
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6\r
+// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+//\r
+\r
+var WshShell = new ActiveXObject( "WScript.Shell" );\r
+var ProcEnv = WshShell.Environment( "Process" );\r
+var PathVal = ProcEnv("PATH");\r
+if ( PathVal.length == 0 ) {\r
+  PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;";\r
+} else {\r
+  PathVal = "S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64;S:/vivado/Vivado/2019.1/bin;" + PathVal;\r
+}\r
+\r
+ProcEnv("PATH") = PathVal;\r
+\r
+var RDScrFP = WScript.ScriptFullName;\r
+var RDScrN = WScript.ScriptName;\r
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );\r
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";\r
+eval( EAInclude(ISEJScriptLib) );\r
+\r
+\r
+ISEStep( "vivado",\r
+         "-log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl" );\r
+\r
+\r
+\r
+function EAInclude( EAInclFilename ) {\r
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );\r
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );\r
+  var EAIFContents = EAInclFile.ReadAll();\r
+  EAInclFile.Close();\r
+  return EAIFContents;\r
+}\r

diff --git a/esdi.runs/synth_1/runme.bat b/esdi.runs/synth_1/runme.bat
new file mode 100644 (file)
index 0000000..bc78723
--- /dev/null
+++ b/esdi.runs/synth_1/runme.bat
@@ -0,0 +1,10 @@
+@echo off\r
+\r
+rem  Vivado (TM)\r
+rem  runme.bat: a Vivado-generated Script\r
+rem  Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+\r
+\r
+set HD_SDIR=%~dp0\r
+cd /d "%HD_SDIR%"\r
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*\r

diff --git a/esdi.runs/synth_1/runme.log b/esdi.runs/synth_1/runme.log
new file mode 100644 (file)
index 0000000..677d299
--- /dev/null
+++ b/esdi.runs/synth_1/runme.log
@@ -0,0 +1,217 @@
+\r
+*** Running vivado\r
+    with args -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl\r
+\r
+\r
+****** Vivado v2019.1 (64-bit)\r
+  **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019\r
+  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019\r
+    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+\r
+source esdi_ctl_phy.tcl -notrace\r
+Command: synth_design -top esdi_ctl_phy -part xc7z007sclg225-1\r
+Starting synth_design\r
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7z007s'\r
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z007s'\r
+INFO: Launching helper process for spawning children vivado processes\r
+INFO: Helper process launched with PID 18332 \r
+---------------------------------------------------------------------------------\r
+Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 600.180 ; gain = 179.551\r
+---------------------------------------------------------------------------------\r
+INFO: [Synth 8-6157] synthesizing module 'esdi_ctl_phy' [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]\r
+INFO: [Synth 8-6155] done synthesizing module 'esdi_ctl_phy' (1#1) [S:/vivado-projects/esdi/esdi/esdi.srcs/sources_1/new/esdi_phy_ctl.v:23]\r
+WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module\r
+---------------------------------------------------------------------------------\r
+Finished Synthesize : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Constraint Validation : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Loading Part and Timing Information\r
+---------------------------------------------------------------------------------\r
+Loading part: xc7z007sclg225-1\r
+---------------------------------------------------------------------------------\r
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 663.480 ; gain = 242.852\r
+---------------------------------------------------------------------------------\r
+INFO: [Device 21-403] Loading part xc7z007sclg225-1\r
+---------------------------------------------------------------------------------\r
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 663.480 ; gain = 242.852\r
+---------------------------------------------------------------------------------\r
+\r
+Report RTL Partitions: \r
++-+--------------+------------+----------+\r
+| |RTL Partition |Replication |Instances |\r
++-+--------------+------------+----------+\r
++-+--------------+------------+----------+\r
+No constraint files found.\r
+---------------------------------------------------------------------------------\r
+Start RTL Component Statistics \r
+---------------------------------------------------------------------------------\r
+Detailed RTL Component Info : \r
+---------------------------------------------------------------------------------\r
+Finished RTL Component Statistics \r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start RTL Hierarchical Component Statistics \r
+---------------------------------------------------------------------------------\r
+Hierarchical RTL Component report \r
+---------------------------------------------------------------------------------\r
+Finished RTL Hierarchical Component Statistics\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Part Resource Summary\r
+---------------------------------------------------------------------------------\r
+Part Resources:\r
+DSPs: 66 (col length:40)\r
+BRAMs: 100 (col length: RAMB18 40 RAMB36 20)\r
+---------------------------------------------------------------------------------\r
+Finished Part Resource Summary\r
+---------------------------------------------------------------------------------\r
+No constraint files found.\r
+---------------------------------------------------------------------------------\r
+Start Cross Boundary and Area Optimization\r
+---------------------------------------------------------------------------------\r
+Warning: Parallel synthesis criteria is not met \r
+WARNING: [Synth 8-3330] design esdi_ctl_phy has an empty top module\r
+---------------------------------------------------------------------------------\r
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+\r
+Report RTL Partitions: \r
++-+--------------+------------+----------+\r
+| |RTL Partition |Replication |Instances |\r
++-+--------------+------------+----------+\r
++-+--------------+------------+----------+\r
+No constraint files found.\r
+---------------------------------------------------------------------------------\r
+Start Timing Optimization\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Timing Optimization : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+\r
+Report RTL Partitions: \r
++-+--------------+------------+----------+\r
+| |RTL Partition |Replication |Instances |\r
++-+--------------+------------+----------+\r
++-+--------------+------------+----------+\r
+---------------------------------------------------------------------------------\r
+Start Technology Mapping\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Technology Mapping : Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+\r
+Report RTL Partitions: \r
++-+--------------+------------+----------+\r
+| |RTL Partition |Replication |Instances |\r
++-+--------------+------------+----------+\r
++-+--------------+------------+----------+\r
+---------------------------------------------------------------------------------\r
+Start IO Insertion\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Flattening Before IO Insertion\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Flattening Before IO Insertion\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Final Netlist Cleanup\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Final Netlist Cleanup\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished IO Insertion : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+\r
+Report Check Netlist: \r
++------+------------------+-------+---------+-------+------------------+\r
+|      |Item              |Errors |Warnings |Status |Description       |\r
++------+------------------+-------+---------+-------+------------------+\r
+|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |\r
++------+------------------+-------+---------+-------+------------------+\r
+---------------------------------------------------------------------------------\r
+Start Renaming Generated Instances\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+\r
+Report RTL Partitions: \r
++-+--------------+------------+----------+\r
+| |RTL Partition |Replication |Instances |\r
++-+--------------+------------+----------+\r
++-+--------------+------------+----------+\r
+---------------------------------------------------------------------------------\r
+Start Rebuilding User Hierarchy\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Renaming Generated Ports\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Handling Custom Attributes\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Renaming Generated Nets\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+---------------------------------------------------------------------------------\r
+Start Writing Synthesis Report\r
+---------------------------------------------------------------------------------\r
+\r
+Report BlackBoxes: \r
++-+--------------+----------+\r
+| |BlackBox name |Instances |\r
++-+--------------+----------+\r
++-+--------------+----------+\r
+\r
+Report Cell Usage: \r
++------+-------------+------+\r
+|      |Cell         |Count |\r
++------+-------------+------+\r
+|1     |esdi_ctl_phy |     1|\r
++------+-------------+------+\r
+\r
+Report Instance Areas: \r
++------+---------+-------+------+\r
+|      |Instance |Module |Cells |\r
++------+---------+-------+------+\r
+|1     |top      |       |     0|\r
++------+---------+-------+------+\r
+---------------------------------------------------------------------------------\r
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+---------------------------------------------------------------------------------\r
+Synthesis finished with 0 errors, 0 critical warnings and 2 warnings.\r
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+Synthesis Optimization Complete : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 794.840 ; gain = 374.211\r
+INFO: [Project 1-571] Translating synthesized netlist\r
+INFO: [Project 1-570] Preparing netlist for logic optimization\r
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000\r
+INFO: [Project 1-111] Unisim Transformation Summary:\r
+No Unisim elements were transformed.\r
+\r
+INFO: [Common 17-83] Releasing license: Synthesis\r
+9 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.\r
+synth_design completed successfully\r
+synth_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:16 . Memory (MB): peak = 903.969 ; gain = 507.191\r
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 903.969 ; gain = 0.000\r
+WARNING: [Constraints 18-5210] No constraints selected for write.\r
+Resolution: This message can indicate that there are no constraints for the design, or it can indicate that the used_in flags are set such that the constraints are ignored. This later case is used when running synth_design to not write synthesis constraints to the resulting checkpoint. Instead, project constraints are read when the synthesized design is opened.\r
+INFO: [Common 17-1381] The checkpoint 'S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.dcp' has been generated.\r
+INFO: [runtcl-4] Executing : report_utilization -file esdi_ctl_phy_utilization_synth.rpt -pb esdi_ctl_phy_utilization_synth.pb\r
+INFO: [Common 17-206] Exiting Vivado at Tue Aug 13 10:39:11 2019...\r

diff --git a/esdi.runs/synth_1/runme.sh b/esdi.runs/synth_1/runme.sh
new file mode 100644 (file)
index 0000000..5fd9210
--- /dev/null
+++ b/esdi.runs/synth_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh\r
+\r
+# \r
+# Vivado(TM)\r
+# runme.sh: a Vivado-generated Runs Script for UNIX\r
+# Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.\r
+# \r
+\r
+echo "This script was generated under a different operating system."\r
+echo "Please update the PATH and LD_LIBRARY_PATH variables below, before executing this script"\r
+exit\r
+\r
+if [ -z "$PATH" ]; then\r
+  PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin\r
+else\r
+  PATH=S:/vivado/SDK/2019.1/bin;S:/vivado/Vivado/2019.1/ids_lite/ISE/bin/nt64;S:/vivado/Vivado/2019.1/ids_lite/ISE/lib/nt64:S:/vivado/Vivado/2019.1/bin:$PATH\r
+fi\r
+export PATH\r
+\r
+if [ -z "$LD_LIBRARY_PATH" ]; then\r
+  LD_LIBRARY_PATH=\r
+else\r
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH\r
+fi\r
+export LD_LIBRARY_PATH\r
+\r
+HD_PWD='S:/vivado-projects/esdi/esdi/esdi.runs/synth_1'\r
+cd "$HD_PWD"\r
+\r
+HD_LOG=runme.log\r
+/bin/touch $HD_LOG\r
+\r
+ISEStep="./ISEWrap.sh"\r
+EAStep()\r
+{\r
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1\r
+     if [ $? -ne 0 ]\r
+     then\r
+         exit\r
+     fi\r
+}\r
+\r
+EAStep vivado -log esdi_ctl_phy.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl\r

diff --git a/esdi.runs/synth_1/vivado.jou b/esdi.runs/synth_1/vivado.jou
new file mode 100644 (file)
index 0000000..7befed9
--- /dev/null
+++ b/esdi.runs/synth_1/vivado.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# Vivado v2019.1 (64-bit)
+# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
+# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
+# Start of session at: Tue Aug 13 10:38:50 2019
+# Process ID: 20424
+# Current directory: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1
+# Command line: vivado.exe -log esdi_ctl_phy.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source esdi_ctl_phy.tcl
+# Log file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1/esdi_ctl_phy.vds
+# Journal file: S:/vivado-projects/esdi/esdi/esdi.runs/synth_1\vivado.jou
+#-----------------------------------------------------------
+source esdi_ctl_phy.tcl -notrace

diff --git a/esdi.runs/synth_1/vivado.pb b/esdi.runs/synth_1/vivado.pb
new file mode 100644 (file)
index 0000000..952d41b
Binary files /dev/null and b/esdi.runs/synth_1/vivado.pb differ

diff --git a/esdi.srcs/sources_1/new/esdi_data_phy.v b/esdi.srcs/sources_1/new/esdi_data_phy.v
new file mode 100644 (file)
index 0000000..ce11539
--- /dev/null
+++ b/esdi.srcs/sources_1/new/esdi_data_phy.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 08/06/2019 11:02:11 PM
+// Design Name: 
+// Module Name: esdi_data_phy
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module esdi_data_phy(
+    input drive_sel,
+    input sector_found,
+    input cmd_done,
+    output addr_mark_en,
+    output write_clk,
+    input read_ref_clk,
+    output write_data,
+    input read_data,
+    input index
+    );
+endmodule

diff --git a/esdi.srcs/sources_1/new/esdi_phy_ctl.v b/esdi.srcs/sources_1/new/esdi_phy_ctl.v
new file mode 100644 (file)
index 0000000..73cefb0
--- /dev/null
+++ b/esdi.srcs/sources_1/new/esdi_phy_ctl.v
@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 08/06/2019 10:50:49 PM
+// Design Name: 
+// Module Name: esdi_phy
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module esdi_ctl_phy (
+    output head_sel_2p3,
+    output head_sel_2p2,
+    output write_gate,
+    input cfg_stat,
+    input xfer_ack,
+    input attn,
+    output head_sel_2p0,
+    input sector_found,
+    output head_sel_2p1,
+    input index,
+    input rdy,
+    output xfer_req,
+    output drive_sel_2p0,
+    output drive_sel_2p1,
+    output drive_sel_2p2,
+    output read_gate,
+    output cmd_data
+    );
+endmodule

diff --git a/esdi.xpr b/esdi.xpr
new file mode 100644 (file)
index 0000000..4153109
--- /dev/null
+++ b/esdi.xpr
@@ -0,0 +1,218 @@
+<?xml version="1.0" encoding="UTF-8"?>\r
+<!-- Product Version: Vivado v2019.1 (64-bit)              -->\r
+<!--                                                         -->\r
+<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.   -->\r
+\r
+<Project Version="7" Minor="40" Path="S:/vivado-projects/esdi/esdi/esdi.xpr">\r
+  <DefaultLaunch Dir="$PRUNDIR"/>\r
+  <Configuration>\r
+    <Option Name="Id" Val="7fbdbefb521848e9abfa9f7f113e6522"/>\r
+    <Option Name="Part" Val="xc7z007sclg225-1"/>\r
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>\r
+    <Option Name="CompiledLibDirXSim" Val=""/>\r
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>\r
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>\r
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>\r
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>\r
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>\r
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>\r
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>\r
+    <Option Name="TargetSimulator" Val="ActiveHDL"/>\r
+    <Option Name="BoardPart" Val="em.avnet.com:minized:part0:1.2"/>\r
+    <Option Name="BoardPartRepoPaths" Val="C:/Users/kremlin/AppData/Roaming/Xilinx/Vivado/2019.1/xhub/board_store"/>\r
+    <Option Name="ActiveSimSet" Val="sim_1"/>\r
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>\r
+    <Option Name="ProjectType" Val="Default"/>\r
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>\r
+    <Option Name="IPCachePermission" Val="read"/>\r
+    <Option Name="IPCachePermission" Val="write"/>\r
+    <Option Name="EnableCoreContainer" Val="FALSE"/>\r
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>\r
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>\r
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>\r
+    <Option Name="EnableBDX" Val="FALSE"/>\r
+    <Option Name="DSAVendor" Val="xilinx"/>\r
+    <Option Name="DSABoardId" Val="zcu106"/>\r
+    <Option Name="DSANumComputeUnits" Val="60"/>\r
+    <Option Name="WTXSimLaunchSim" Val="0"/>\r
+    <Option Name="WTModelSimLaunchSim" Val="0"/>\r
+    <Option Name="WTQuestaLaunchSim" Val="0"/>\r
+    <Option Name="WTIesLaunchSim" Val="0"/>\r
+    <Option Name="WTVcsLaunchSim" Val="0"/>\r
+    <Option Name="WTRivieraLaunchSim" Val="0"/>\r
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>\r
+    <Option Name="WTXSimExportSim" Val="0"/>\r
+    <Option Name="WTModelSimExportSim" Val="0"/>\r
+    <Option Name="WTQuestaExportSim" Val="0"/>\r
+    <Option Name="WTIesExportSim" Val="0"/>\r
+    <Option Name="WTVcsExportSim" Val="0"/>\r
+    <Option Name="WTRivieraExportSim" Val="0"/>\r
+    <Option Name="WTActivehdlExportSim" Val="0"/>\r
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>\r
+    <Option Name="XSimRadix" Val="hex"/>\r
+    <Option Name="XSimTimeUnit" Val="ns"/>\r
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>\r
+    <Option Name="XSimTraceLimit" Val="65536"/>\r
+    <Option Name="SimTypes" Val="rtl"/>\r
+    <Option Name="SimTypes" Val="bfm"/>\r
+    <Option Name="SimTypes" Val="tlm"/>\r
+    <Option Name="SimTypes" Val="tlm_dpi"/>\r
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>\r
+  </Configuration>\r
+  <FileSets Version="1" Minor="31">\r
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">\r
+      <Filter Type="Srcs"/>\r
+      <File Path="$PSRCDIR/sources_1/new/esdi_phy_ctl.v">\r
+        <FileInfo>\r
+          <Attr Name="UsedIn" Val="synthesis"/>\r
+          <Attr Name="UsedIn" Val="implementation"/>\r
+          <Attr Name="UsedIn" Val="simulation"/>\r
+        </FileInfo>\r
+      </File>\r
+      <File Path="$PSRCDIR/sources_1/new/esdi_data_phy.v">\r
+        <FileInfo>\r
+          <Attr Name="AutoDisabled" Val="1"/>\r
+          <Attr Name="UsedIn" Val="synthesis"/>\r
+          <Attr Name="UsedIn" Val="implementation"/>\r
+          <Attr Name="UsedIn" Val="simulation"/>\r
+        </FileInfo>\r
+      </File>\r
+      <Config>\r
+        <Option Name="DesignMode" Val="RTL"/>\r
+        <Option Name="TopModule" Val="esdi_ctl_phy"/>\r
+        <Option Name="TopAutoSet" Val="TRUE"/>\r
+      </Config>\r
+    </FileSet>\r
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">\r
+      <Filter Type="Constrs"/>\r
+      <Config>\r
+        <Option Name="ConstrsType" Val="XDC"/>\r
+      </Config>\r
+    </FileSet>\r
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">\r
+      <Filter Type="Srcs"/>\r
+      <Config>\r
+        <Option Name="DesignMode" Val="RTL"/>\r
+        <Option Name="TopModule" Val="esdi_ctl_phy"/>\r
+        <Option Name="TopLib" Val="xil_defaultlib"/>\r
+        <Option Name="TopAutoSet" Val="TRUE"/>\r
+        <Option Name="TransportPathDelay" Val="0"/>\r
+        <Option Name="TransportIntDelay" Val="0"/>\r
+        <Option Name="SrcSet" Val="sources_1"/>\r
+      </Config>\r
+    </FileSet>\r
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">\r
+      <Filter Type="Utils"/>\r
+      <Config>\r
+        <Option Name="TopAutoSet" Val="TRUE"/>\r
+      </Config>\r
+    </FileSet>\r
+  </FileSets>\r
+  <Simulators>\r
+    <Simulator Name="XSim">\r
+      <Option Name="Description" Val="Vivado Simulator"/>\r
+      <Option Name="CompiledLib" Val="0"/>\r
+    </Simulator>\r
+    <Simulator Name="ModelSim">\r
+      <Option Name="Description" Val="ModelSim Simulator"/>\r
+    </Simulator>\r
+    <Simulator Name="Questa">\r
+      <Option Name="Description" Val="Questa Advanced Simulator"/>\r
+    </Simulator>\r
+    <Simulator Name="Riviera">\r
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>\r
+    </Simulator>\r
+    <Simulator Name="ActiveHDL">\r
+      <Option Name="Description" Val="Active-HDL Simulator"/>\r
+    </Simulator>\r
+  </Simulators>\r
+  <Runs Version="1" Minor="10">\r
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z007sclg225-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">\r
+      <Strategy Version="1" Minor="2">\r
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">\r
+          <Desc>Vivado Synthesis Defaults</Desc>\r
+        </StratHandle>\r
+        <Step Id="synth_design"/>\r
+      </Strategy>\r
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>\r
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>\r
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>\r
+    </Run>\r
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z007sclg225-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">\r
+      <Strategy Version="1" Minor="2">\r
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">\r
+          <Desc>Default settings for Implementation.</Desc>\r
+        </StratHandle>\r
+        <Step Id="init_design"/>\r
+        <Step Id="opt_design"/>\r
+        <Step Id="power_opt_design"/>\r
+        <Step Id="place_design"/>\r
+        <Step Id="post_place_power_opt_design"/>\r
+        <Step Id="phys_opt_design"/>\r
+        <Step Id="route_design"/>\r
+        <Step Id="post_route_phys_opt_design"/>\r
+        <Step Id="write_bitstream"/>\r
+      </Strategy>\r
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>\r
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>\r
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>\r
+    </Run>\r
+  </Runs>\r
+  <Board>\r
+    <Jumpers/>\r
+  </Board>\r
+  <DashboardSummary Version="1" Minor="0">\r
+    <Dashboards>\r
+      <Dashboard Name="default_dashboard">\r
+        <Gadgets>\r
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>\r
+          </Gadget>\r
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>\r
+          </Gadget>\r
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>\r
+          </Gadget>\r
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>\r
+          </Gadget>\r
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>\r
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>\r
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>\r
+          </Gadget>\r
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">\r
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>\r
+          </Gadget>\r
+        </Gadgets>\r
+      </Dashboard>\r
+      <CurrentDashboard>default_dashboard</CurrentDashboard>\r
+    </Dashboards>\r
+  </DashboardSummary>\r
+  <BootPmcSettings Version="1" Minor="0">\r
+    <Parameters>\r
+      <Parameter Name="PMC_CDO.ATTRS.LOADADDR" Value="" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.QSPI_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.QSPI_FB_CLK" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.QSPI_FREQ" Value="300" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.QSPI_BUS_WIDTH" Value="x1" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.QSPI_DATA_MODE" Value="Single" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD0_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD0_FREQ" Value="200" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD0_SLOT_TYPE" Value="SD 2.0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD0_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD1_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD1_FREQ" Value="200" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD1_SLOT_TYPE" Value="SD 2.0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SD1_DATA_TRANSFER_MODE" Value="4Bit" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.OSPI_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.OSPI_FREQ" Value="300" Type="string"/>\r
+      <Parameter Name="BOOT.USB_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SMAP_ENABLE" Value="0" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.SMAP_DATA_WIDTH" Value="32 Bit" Type="string"/>\r
+      <Parameter Name="BOOT.PMC.OSC_FREQ" Value="33.333" Type="string"/>\r
+      <Parameter Name="BOOT.SECONDARY.PCIE_ENABLE" Value="0" Type="string"/>\r
+    </Parameters>\r
+  </BootPmcSettings>\r
+</Project>\r